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Page 24

Epson Research and Development

Vancouver Design Center

S1D13513

S5U13513P00C100 Evaluation Board User Manual

X78A-G-003-01

Issue Date: 2010/09/06

Revision 1.1

6  Schematic Diagrams

Figure 6-1: S5U13513P00C100 Schematics (1 of 4)

5

5

4

4

3

3

2

2

1

1

D

D

C

C

B

B

A

A

513_T

D

O

513_T

D

I

FP

D

A

T1

2

FP

D

A

T0

DB

1

2

FP

D

A

T2

0

513_T

C

K

FP

D

A

T1

3

DB

1

0

AB

0

FP

D

A

T1

5

FP

D

A

T4

DB

1

3

AB

1

6

AB

1

7

FP

D

A

T7

DB

8

DB

2

AB

5

FP

D

A

T1

6

DB

1

4

AB

1

5

AB

8

AB

6

FP

D

A

T2

2

FP

D

A

T9

FP

D

A

T5

DB

1

5

DB

9

FP

D

A

T8

DB

1

1

AB

1

2

AB

1

1

AB

4

AB

1

9

FP

D

A

T1

1

FP

D

A

T2

FP

D

A

T1

8

AB

2

0

513_T

D

I

513_T

M

S

DB

3

FP

D

A

T1

7

AB

7

513_T

C

K

FP

D

A

T2

3

FP

D

A

T2

1

FP

D

A

T3

AB

1

FP

D

A

T1

0

FP

D

A

T6

DB

6

DB

5

DB

1

AB

1

3

AB

3

AB

1

8

FP

D

A

T1

4

FP

D

A

T1

AB

1

4

513_T

M

S

DB

7

DB

0

AB

2

513_T

D

O

AB

1

0

FP

D

A

T1

9

DB

4

AB

9

ME

MD

Q

2

0

ME

MD

Q

2

9

ME

MD

Q

4

ME

MD

Q

1

8

ME

MA

4

ME

MA

5

ME

MA

6

ME

MD

Q

3

ME

MD

Q

9

ME

MD

Q

2

8

ME

MD

Q

1

3

ME

MD

Q

3

1

ME

MD

Q

2

2

ME

MD

Q

2

7

ME

MA

3

ME

MD

Q

1

2

ME

MD

Q

1

6

ME

MD

Q

2

4

ME

MD

Q

2

5

ME

MA

8

ME

MD

Q

1

1

ME

MD

Q

1

4

ME

MD

Q

1

0

ME

MA

0

ME

MD

Q

5

ME

MA

1

0

ME

MD

Q

1

7

ME

MA

2

ME

MA

7

ME

MD

Q

2

1

ME

MA

1

1

ME

MA

1

ME

MD

Q

1

5

ME

MD

Q

2

3

ME

MD

Q

6

ME

MD

Q

1

ME

MD

Q

3

0

ME

MA

9

ME

MD

Q

1

9

ME

MD

Q

2

6

ME

MD

Q

8

ME

MD

Q

0

ME

MD

Q

2

ME

MD

Q

7

513_T

R

S

T

513_T

R

S

T

CI

O

V

D

D

1

1.

8V

D

D

CO

RE

CO

RE

HI

O

V

DD

HV

D

D

1

PI

O

V

D

D

HV

D

D

2

HV

DD

4

HV

D

D

5

HV

D

D

2

HV

DD3

OS

C

1

OS

C

2

CI

O

V

DD

1

HV

D

D

1

P

LL1

P

LL2

OS

C

1

1.

8V

D

D

PL

L

2

1.

8

V

D

D

OS

C

2

1.

8

V

D

D

3.

3V

D

D

HV

D

D

5

CI

O

V

DD

1

HV

D

D

4

CIO

V

DD

2

HV

DD3

1.

8V

D

D

PL

L

1

GN

D

1

GN

D

2

GN

D

1

GN

D

2

GN

D

3

GN

D

4

GN

D

3

GN

D

4

3.

3V

D

D

3.

3V

D

D

3.

3V

D

D

3.

3V

D

D

F

P

D

A

T

[23:

0]

4

FP

FR

A

M

E

4

FP

L

IN

E

4

FP

S

H

IF

T

4

F

P

DRD

Y

4

A

B

[20:

0]

3

D

B

[15:

0]

3

OS

C

O

1

2

OS

C

O

2

2

OS

C

I1

2

OS

C

I2

2

CL

K

I3

2

R

ESET

#

2

INT

1

#

3

CS

#

3

RD

#

3

WE

0

#

3

BS

#

3

BD

IP

#

3

INT

2

#

3

M/

R

#

3

RD

/W

R#

3

BU

S

C

L

K

3

WE

1

#

3

WA

IT

#

3

B

URS

T

#

3

ME

MC

S

#

2

ME

MW

E

#

2

M

E

M

A

[11:

0]

2

ME

MC

A

S

#

2

ME

MR

A

S

#

2

ME

MD

Q

M

2

2

ME

MD

Q

M

0

2

ME

MD

Q

M

3

2

ME

MD

Q

M

1

2

ME

MC

K

E

2

ME

MC

L

K

2

ME

MB

A

0

2

M

E

M

D

Q

[31:

0]

2

ME

MB

A

1

2

GP

IO

G

0

4

GP

IO

G

1

4

GP

IO

G

2

4

GP

IO

G

3

4

GP

IO

G

4

4

GP

IO

A

0

4

GP

IO

A

1

4

GP

IO

A

2

4

GP

IO

A

3

4

GP

IO

A

4

4

GP

IO

A

5

4

GP

IO

A

6

4

GP

IO

A

7

4

GP

IO

B

0

4

GP

IO

B

1

4

GP

IO

B

2

4

GP

IO

B

3

4

GP

IO

B

4

4

GP

IO

B

5

4

GP

IO

B

6

4

GP

IO

B

7

4

GP

IO

C

0

4

GP

IO

C

1

4

GP

IO

C

2

4

GP

IO

C

3

4

GP

IO

C

4

4

GP

IO

C

5

4

GP

IO

C

6

4

GP

IO

C

7

4

GP

IO

D

0

4

GP

IO

D

1

4

GP

IO

D

2

4

GP

IO

D

3

4

Ti

tl

e

Si

z

e

D

o

c

u

m

e

nt

 N

u

m

ber

Re

v

Da

te

:

S

h

eet

of

<D

o

c

>

1

.0

S

1

D

13513 P

B

G

A

256

C

14

T

hur

s

day

, J

anu

ar

y

 04,

 20

07

Ti

tl

e

Si

z

e

D

o

c

u

m

e

nt

 N

u

m

ber

Re

v

Da

te

:

S

h

eet

of

<D

o

c

>

1

.0

S

1

D

13513 P

B

G

A

256

C

14

T

hur

s

day

, J

anu

ar

y

 04,

 20

07

Ti

tl

e

Si

z

e

D

o

c

u

m

e

nt

 N

u

m

ber

Re

v

Da

te

:

S

h

eet

of

<D

o

c

>

1

.0

S

1

D

13513 P

B

G

A

256

C

14

T

hur

s

day

, J

anu

ar

y

 04,

 20

07

J

T

AG /

 Boundary

Sc

an Port

P

lac

e a 0.

01u

F

 and a 0.

1u

F

 c

ap on 

eac

h

C

O

R

E

V

D

D

 p

o

w

e

r pi

n of

 t

he S

1

D

13513

P

lac

e a 0.

01uF

 a

nd a 0.

1uF

 c

ap on e

a

c

h

H

V

D

D

1

 pow

er

 pin of

 t

h

e S

1

D

135

13

P

lac

e a

 0.

01uF

 and 

a 0.

1uF

 c

a

p on eac

h

H

V

D

D

2 p

o

w

e

r pi

n of

 t

he S

1

D

13513

P

lac

e 33 O

h

m

 s

e

ri

es

 s

ourc

e

 t

e

rm

inat

io

n

re

s

is

to

rs

 as

 c

los

to

 t

he S

1

D

13513 as

p

o

s

s

ibl

e.

P

la

c

e a 0.

0

1uF

 and a 0

.1uF

 c

ap 

on eac

h

O

S

C

V

D

D

1 po

w

e

r pi

n of

 t

he S

1

D

13513

P

lac

e a 0.

01

uF

 and a 0.

1uF

 c

ap o

n

 eac

h

O

S

C

V

D

D

2 pow

er pi

n

 of

 t

he S

1

D

13513

P

lac

e

 a 0.

01uF

 an

d a 0.

1uF

 c

ap on ea

c

h

H

V

D

D

5

 pow

e

pi

n of

 t

h

e S

1

D

135

13

P

lac

e a 0.

01uF

 a

nd a 0.

1uF

 c

ap on e

a

c

h

H

V

D

D

4

 pow

er

 pin of

 t

h

e S

1

D

135

13

P

lac

e a 0.

01uF

 and a 

0.

1uF

 c

a

p

 on eac

h

H

V

D

D

3 pow

er pi

n

 of

 t

he S

1

D

13513

R5

3

33

 1

%

R5

3

33

 1

%

R3

1

0

R3

1

0

R1

8

33

 1

%

R1

8

33

 1

%

R3

5

33

 1

%

R3

5

33

 1

%

R6

6

10k

R6

6

10k

R5

2

33

 1

%

R5

2

33

 1

%

C7

0.

1uF

C7

0.

1uF

R1

7

33

 1

%

R1

7

33

 1

%

C1

2

0.

01uF

C1

2

0.

01uF

C5

0

0.

1uF

C5

0

0.

1uF

R3

2

33

 1

%

R3

2

33

 1

%

R1

6

33

 1

%

R1

6

33

 1

%

R7

0

0

R7

0

0

C1

7

0.

01

uF

C1

7

0.

01

uF

C5

4

0.

01uF

C5

4

0.

01uF

R6

1

10k

R6

1

10k

R3

0

33

 1

%

R3

0

33

 1

%

C4

1

0.

01uF

C4

1

0.

01uF

R5

1

33

 1

%

R5

1

33

 1

%

L1

F

e

rri

te

L1

F

e

rri

te

C6

0

0.

01uF

C6

0

0.

01uF

R1

5

33

 1

%

R1

5

33

 1

%

U1

S

1

D1

3513 PB

G

A

25

6

U1

S

1

D1

3513 PB

G

A

25

6

AB1

A2

AB2

B2

AB3

A3

AB4

B3

AB5

C4

AB6

B4

AB7

A4

AB8

A5

AB9

B5

AB1

0

C5

AB1

1

C6

AB1

2

D6

AB1

3

B6

AB1

4

A6

AB1

5

A7

AB1

6

C7

DB

0

G3

DB

1

F1

DB

2

F7

DB

3

F2

DB

4

F5

DB

5

F3

DB

6

F4

DB

7

E1

DB

8

E5

DB

9

E3

DB

1

0

E4

DB

1

1

D2

DB

1

2

D3

DB

1

3

D1

DB

1

4

C2

DB

1

5

C1

CL

K

I

K1

CS

#

G6

M/

R

#

G1

IN

T

1

#

H5

RD

#

H4

WE

0

#

H1

WE

1

#

G5

RD

/W

R#

H2

RE

S

E

T

#

J3

WA

IT

#

J2

CN

F

0

J1

5

CN

F

1

J1

3

CN

F

2

K1

1

FP

D

A

T0

M7

FP

D

A

T1

N7

FP

D

A

T2

T7

FP

D

A

T3

R7

FP

D

A

T4

P7

FP

D

A

T5

L7

FP

D

A

T6

M6

FP

D

A

T7

K6

FP

D

A

T8

R6

FP

D

A

T9

P6

FP

D

A

T1

0

M5

FP

D

A

T1

1

N5

FP

D

A

T1

2

T5

FP

D

A

T1

3

T4

FP

D

A

T1

4

R4

FP

D

A

T1

5

T2

FP

D

A

T1

6

P4

FP

D

A

T1

7

N4

FP

FR

A

M

E

R8

FP

L

IN

E

T8

F

PSH

IF

T

P8

F

P

DR

DY

M8

GP

IO

G0

L9

GP

IO

G1

P9

GP

IO

G2

R9

GP

IO

G3

T9

AB1

7

E6

GP

IO

G4

N8

CN

F

3

J1

4

CN

F

4

K1

6

CN

F

5

K1

2

CN

F

6

K1

5

AB1

8

D7

CN

F

7

L16

TE

S

T

E

N

L15

TR

S

T

P1

3

TM

S

R1

4

TD

O

R1

5

TD

I

N1

2

TC

K

P1

2

VC

P1

N1

M

E

M

C

AS#

G1

4

M

E

M

R

AS#

G1

5

ME

MB

A

0

F1

6

ME

MB

A

1

G1

2

ME

MC

S

#

H1

1

ME

M

W

E

#

G1

6

ME

MC

K

E

H1

6

ME

MC

L

K

J1

6

ME

MD

Q

M

0

H1

3

ME

MD

Q

M

1

H1

4

CORE

VD

D

C3

CORE

VD

D

F6

CORE

VD

D

L11

CORE

VD

D

F11

CORE

VD

D

C14

CORE

VD

D

K3

HVD

D1

D5

VSS

G7

VSS

G8

VSS

G9

VSS

D4

VSS

D8

VSS

D13

VSS

G10

VSS

H7

VSS

H8

VSS

H10

VSS

G13

OSC

VS

S1

L3

OSC

VS

S2

M4

PLLV

SS

1

N2

PLLV

SS

2

R2

CORE

VD

D

L6

VSS

H9

CORE

VD

D

P3

CORE

VD

D

P14

HVD

D1

E2

HVD

D1

G4

HVD

D2

L5

HVD

D2

L8

HVD

D2

T6

HVD

D3

R11

HVD

D4

L12

HVD

D4

M13

HVD

D4

T15

HVD

D5

B9

HVD

D5

C12

HVD

D5

E15

HVD

D5

G11

HVD

D5

H12

HVD

D5

J12

OS

CVDD1

L4

OS

CVDD2

M3

PL

LV

DD1

P1

PL

LV

DD2

P2

AB0

B1

AB1

9

B7

AB2

0

E7

FP

D

A

T1

8

R5

FP

D

A

T1

9

K5

FP

D

A

T2

0

P5

FP

D

A

T2

1

T3

FP

D

A

T2

2

R3

FP

D

A

T2

3

K4

BU

SC

L

K

G2

IN

T

2

#

H6

BS#

H3

Re

s

e

rv

e

d

J5

BU

R

S

T

#

J4

BD

IP

#

J6

VC

P2

R1

VSS

J1

VSS

J7

VSS

J8

VSS

J9

VSS

J10

VSS

K2

VSS

K7

VSS

K8

VSS

K9

VSS

K10

VSS

K13

VSS

N3

VSS

N6

VSS

N9

VSS

N13

VSS

T1

VSS

A16

VSS

A1

VSS

T16

CN

F

8

K1

4

ME

MD

Q

0

C9

ME

MD

Q

1

A1

0

ME

MD

Q

2

B1

0

ME

MD

Q

3

C1

0

ME

MD

Q

4

B1

1

ME

MD

Q

5

D1

1

ME

MD

Q

6

E1

2

ME

MD

Q

7

A1

2

ME

MD

Q

8

D1

2

ME

MD

Q

9

C1

3

ME

MD

Q

1

0

A1

4

ME

MD

Q

1

1

B1

5

ME

MD

Q

1

2

B1

6

ME

MD

Q

1

3

D1

4

ME

MD

Q

1

4

D1

5

ME

MD

Q

1

5

E1

4

ME

MD

Q

1

6

D9

ME

MD

Q

1

7

F1

0

ME

MD

Q

1

8

E1

0

ME

MD

Q

1

9

D1

0

ME

MD

Q

2

0

E1

1

ME

MD

Q

2

1

C1

1

ME

MD

Q

2

2

A1

1

ME

MD

Q

2

3

B1

2

ME

MD

Q

2

4

A1

3

ME

MD

Q

2

5

B1

3

ME

MD

Q

2

6

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Содержание S5U13513P00C100

Страница 1: ... and use this document but only for your own use in evaluating Seiko Epson EPSON products You may not modify the document Epson Research and Development Inc disclaims any representation that the contents of this document are accurate or current The Programs Technologies described in this document may contain material protected under U S and or International Patent laws EPSON is a registered tradem...

Страница 2: ...Page 2 Epson Research and Development Vancouver Design Center S1D13513 S5U13513P00C100 Evaluation Board User Manual X78A G 003 01 Issue Date 2010 09 06 Revision 1 1 ...

Страница 3: ...ower 13 4 2 Clocks 14 4 3 Reset 14 4 4 Host Interface 15 4 4 1 Connecting to the Epson S5U13U00P00C100 USB Adapter Board 15 4 4 2 Connecting to the Epson PC Card Extender Board 15 4 4 3 Direct Host Bus Interface Support 16 4 5 LCD Panel Interface 17 4 6 Camera Interface 18 4 7 YUV Output for TV Display 19 4 8 Keypad Interface 19 4 9 PWM Outputs 19 4 10 GPIO Connections 19 4 11 JTAG Connector 20 5 ...

Страница 4: ...Page 4 Epson Research and Development Vancouver Design Center S1D13513 S5U13513P00C100 Evaluation Board User Manual X78A G 003 01 Issue Date 2010 09 06 Revision 1 1 ...

Страница 5: ... a laptop or desktop computer via USB 2 0 With some minor modifications it is possible to connect the S5U13513P00C100 evaluation board to a Epson PC Card Extender board instead of a USB Adapter board The S5U13513P00C100 evaluation board can also be used with many other native platforms via the host connectors which provide the appropriate signals to support a variety of CPUs This user manual is up...

Страница 6: ...DRAM selectable as 8MB x 32 bit or 8MB x 16 bit Headers for connection to the S5U13U00P00C100 USB Adapter board or to the PC Card Extender board Headers for connecting to various Host Bus Interfaces Headers for connecting to LCD panels Headers for connecting to cameras On board 10MHz crystal used for OSC1 clock input On board 27MHz crystal used for OSC2 clock input 14 pin DIP socket used to instal...

Страница 7: ... switch SW1 on the S5U13513P00C100 Figure 3 1 Configuration DIP Switch SW1 Location All S1D13513 configuration inputs CNF 8 0 are fully configurable using DIP switch SW1 as described below Table 3 1 Summary of Power On Reset Options SDU13513B00C SW1 10 1 Config S1D13513 CNF 8 0 Config Power On Reset State 1 ON 0 OFF SW1 10 Not used SW1 9 8 CNF 8 7 00b CLKI3 is the PLL1 clock source 01b BUSCLK is t...

Страница 8: ... 01000b Parallel Direct 80 Type 2 2 CS 01001b Reserved 01010b Reserved 01011b Reserved 01100b Parallel Direct 80 Type 1 2 CS 01101b Parallel Direct 68 2 CS 01110b Reserved 01111b Reserved 10000b Serial on HVDD1 Data valid on falling edge 10001b Serial on HVDD2 Data valid on falling edge 10010b Reserved 10011b Reserved 10100b Reserved 10101b Reserved 10110b Reserved 10111b Reserved 11000b Serial on...

Страница 9: ...010b MIPS ISA Little Endian Active HIgh WAIT with tri state 01011b Reserved 01100b MC68000 Big Endian Active High WAIT with tri state 01101b Reserved 01110b MC68030 Big Endian Active High WAIT with tri state 01111b Reserved 10000b PR31500 31700 TX3912 Little Endian Active Low WAIT with tri state 16 bit memory accesses only 10001b PR31500 31700 TX3912 Little Endian Active Low WAIT always driven 16 ...

Страница 10: ...ry Jumper Function Position 1 2 Position 2 3 No Jumper JP1 COREVDD Normal COREVDD current measurement JP2 PLLVDD1 Normal PLLVDD1 current measurement JP3 PLLVDD2 Normal PLLVDD2 current measurement JP4 OSCVDD1 Normal OSCVDD1 current measurement JP5 OSCVDD2 Normal OSCVDD2 current measurement JP6 HVDD1 Normal HVDD1 current measurement JP7 HVDD2 Normal HVDD2 current measurement JP8 HVDD3 Normal HVDD3 c...

Страница 11: ...is selected When no jumper is installed the current consumption for each power supply can be measured by connecting an ammeter to pin 1 and 2 of the jumper The jumper associated to each power supply is as follows JP1 for COREVDD JP2 for PLLVDD1 JP3 for PLLVDD2 JP4 for OSCVDD1 JP5 for OSCVDD2 JP6 for HVDD1 Host interface JP7 for HVDD2 LCD Panel interface JP8 for HVDD3 Camera2 interface JP9 for HVDD...

Страница 12: ...dth of the external SDRAM When the jumper is at position 1 2 the external SDRAM is 32 bit wide and memory size is 32MB The memory consists of 2 chips in parallel each 16MB and 16 bit wide When the jumper is at position 2 3 the external SDRAM is 16 bit wide and memory size is 16MB In this position one memory chip is disabled and only one chip is active 16MB and 16 bit wide Figure 3 3 Configuration ...

Страница 13: ...CD panels 4 1 3 S1D13513 Power The S1D13513 Display Controller requires 1 8V and 3 3V power supplies 1 8V power is provided by the on board linear voltage regulator It is used for CoreVDD PLLVDD1 PLLVDD2 OSCVDD1 OSCVDD2 3 3V power must be provided by the external power supply It is used for HVDD1 host interface HIOVDD HVDD2 LCD panel interface PIOVDD HVDD3 camera 2 interface CIOVDD2 HVDD4 camera 1...

Страница 14: ...13P00C100 evaluation board OSC1 and OSC2 use crystals 10MHz for OSC1 and 27MHz for OSC2 For the S5U13513P00C100 evaluation board CLKI3 is not used and is pulled to ground by a 10kΩ resistor However if CLKI3 is required connect a 14 pin DIP package oscillator in the Y1 footprint For the S5U13513P00C100 evaluation board BUSCLK is not used and is pulled to ground by a 10kΩ resistor However if BUSCLK ...

Страница 15: ...power supply and some modifications to the S5U13513P00C100 board The modifications required for the S5U13513P00C100 board are 1 Remove R107 and R108 0 ohm resistors size 0603 2 Remove R109 and R112 0 ohm resistors size 0402 3 Populate R110 and R111 with 0 ohm resistors size 0402 or short the pads on the board 4 Set DIP switch SW1 5 1 to 00100b CNF 4 0 00100b to select Parallel Direct 80 Type 1 1CS...

Страница 16: ...tors H2 and H3 which allow the S5U13513P00C100 to be connected to a variety of development platforms However connectors H2 and H3 are not populated on the S5U13513P00C100 evaluation board If connectors H2 and H3 are added all host interface signals must match HVDD1 of the S1D13513 For the maximum minimum values of the voltages refer to the S1D13513 Hardware Functional Specification document number...

Страница 17: ...2 For the pinout of connectors H4 and H5 see Schematic Diagrams on page 24 On the evaluation board there is an adjustable 6 24V 40mA max power supply This voltage is provided only on connector H4 it is not used elsewhere on the board It is intended for use to power the LED backlight on some LCD panels The voltage is adjusted by the R106 pot Note For LCD panels that use CCFL backlight an external p...

Страница 18: ...ut pins GPIOA 7 0 and GPIOB 7 0 may be configured as GPIO pins Camera2 interface pins Keypad interface pins or PWM output pins For detailed S1D13513 GPIO pin mapping refer to the S1D13513 Hardware Functional Specification document number X78B A 001 xx Connector H6 and H7 may be used to evaluate any function for which the GPIOA 7 0 GPIOB 7 0 GPIOC 7 0 GPIOD 3 0 can be configured The S1D13513 has an...

Страница 19: ...1D13513 has 4 PWM outputs which may be used to control the brightness of 4 LEDs It also has an input AUDIN which is used to control the overall operation of the PWM outputs The PWM output function is multiplexed on the GPIOA 7 5 and GPIOB 7 pins AUDIN is multiplexed on the GPIOD 3 pin These pins are routed to connector H6 and H7 4 10 GPIO Connections The S1D13513 Display Controller GPIO pins have ...

Страница 20: ...06 Revision 1 1 4 11 JTAG Connector The S1D13513 design includes a JTAG interface All the JTAG signals are available on connector H1 however connector H1 is not populated on the board For the pinout of connector H1 see Schematic Diagrams on page 24 The following diagram shows the location of the JTAG connector H1 Figure 4 4 JTAG Connector Location H1 ...

Страница 21: ...C91 C92 C93 C94 C95 C96 0 01uF Yageo America 0402ZRY5V7BB103 3 2 C20 C23 1nF Yageo America 04022R102K9B20D 4 2 C21 C24 10uF Panasonic ECG ECJ CV50J106M 5 4 C61 C62 C63 C64 18pF Panasonic ECG ECJ 0EC1H180J 6 2 C67 C68 10uF Panasonic ECG ECJ 2FB1A106K 7 2 C97 C99 1uF Panasonic ECG ECJ 0EB0J105M 8 1 C101 4 7uF 10V T Kemet T491B475K010AS 9 1 C102 10pF Panasonic ECG ECJ 0EC1H100D 10 1 C103 1uF 50V TDK ...

Страница 22: ... R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 R30 R32 R35 R36 R37 R38 R39 R40 R41 R42 R43 R44 R45 R46 R47 R48 R49 R50 R51 R52 R53 R54 R55 R56 R57 R58 R68 R69 R77 33 1 26 7 R31 R33 R34 R70 R96 R107 R108 0 27 12 R59 R60 R61 R62 R63 R64 R65 R66 R67 R78 R79 R81 10k 28 6 R71 R76 R80 R102 R109 R112 0 29 2 R72 R73 1M 30 2 R74 R75 220 31 1 R82 270 1 32 15 R83 R85 R87 R88...

Страница 23: ...RE SMT Keystone 5015 42 0 T1 TP SIP 43 1 U1 S1D13513 PBGA256 44 2 U2 U3 IS42S16800D 7TL alternate Micron MT48LC8M16A2P 7E ISSI IS42S16800D 7TL 45 1 U4 TPS3801L30DCKR IC 2 64V SUPPLY MON SOT 323 5 Texas Instruments TPS3801L30DCKR 46 1 U5 MIC37100 1 8WS Alternate MIC39100 1 8WS Micrel MIC37100 1 8WS 47 1 U6 TPS61040 IC CONV DC DC BOOST LP SOT 23 5 TI TPS61040DVBR 48 1 X1 MA 506 10 0000M 49 1 X2 MA 5...

Страница 24: ...8 VSS D13 VSS G10 VSS H7 VSS H8 VSS H10 VSS G13 OSCVSS1 L3 OSCVSS2 M4 PLLVSS1 N2 PLLVSS2 R2 COREVDD L6 VSS H9 COREVDD P3 COREVDD P14 HVDD1 E2 HVDD1 G4 HVDD2 L5 HVDD2 L8 HVDD2 T6 HVDD3 R11 HVDD4 L12 HVDD4 M13 HVDD4 T15 HVDD5 B9 HVDD5 C12 HVDD5 E15 HVDD5 G11 HVDD5 H12 HVDD5 J12 OSCVDD1 L4 OSCVDD2 M3 PLLVDD1 P1 PLLVDD2 P2 AB0 B1 AB19 B7 AB20 E7 FPDAT18 R5 FPDAT19 K5 FPDAT20 P5 FPDAT21 T3 FPDAT22 R3 F...

Страница 25: ...000M X1 MA 506 10 0000M XIN 1 XOUT 4 NC 2 NC 3 C83 0 01uF C83 0 01uF C77 0 1uF C77 0 1uF R76 0 R76 0 C63 18pF C63 18pF C89 0 01uF C89 0 01uF C72 0 1uF C72 0 1uF C95 0 01uF C95 0 01uF R78 10k R78 10k C105 0 1uF C105 0 1uF C65 0 1uF C65 0 1uF C84 0 01uF C84 0 01uF C78 0 1uF C78 0 1uF SW2 SW TACT SPST SW2 SW TACT SPST 2 4 3 1 C90 0 01uF C90 0 01uF C62 18pF C62 18pF C73 0 1uF C73 0 1uF C96 0 01uF C96 ...

Страница 26: ...Title Size Document Number Rev Date Sheet of Doc 1 0 Host connectors B 3 4 Friday January 19 2007 Title Size Document Number Rev Date Sheet of Doc 1 0 Host connectors B 3 4 Friday January 19 2007 This resistor is used to pull down BUSCLK input when it is not used If BUSCLK input is used then this resistor can be removed R109 0 R109 0 R108 0 R108 0 R110 NP R110 NP TPGND3 TP_SMT TPGND3 TP_SMT 1 R111...

Страница 27: ...ber Rev Date Sheet of Doc 1 0 LCD and Camera GPIO connectors B 4 4 Friday January 19 2007 Place these capacitors close to pin 15 of the header These resistors are to prevent GPIOA 7 0 and GPIOB7 GPIOB 4 0 from floating if they are not used GPIOB 6 5 are pulled up If any of GPIOA 7 0 GPIOB7 or GPIOB 4 0 are used the corresponding pull down resistor may be removed Place these capacitors close to pin...

Страница 28: ... and Development Vancouver Design Center S1D13513 S5U13513P00C100 Evaluation Board User Manual X78A G 003 01 Issue Date 2010 09 06 Revision 1 1 7 S5U13513P00C100 Board Layout Figure 7 1 S5U13513P00C100 Board Layout Top View ...

Страница 29: ...search and Development Page 29 Vancouver Design Center S5U13513P00C100 Evaluation Board User Manual S1D13513 Issue Date 2010 09 06 X78A G 003 01 Revision 1 1 Figure 7 2 S5U13513P00C100 Board Layout Bottom View ...

Страница 30: ...luation Board User Manual X78A G 003 01 Issue Date 2010 09 06 Revision 1 1 8 References 8 1 Documents Epson Research and Development Inc S1D13513 Hardware Functional Specification document number X78B A 001 xx 8 2 Document Sources Epson Research and Development Website http www erd epson com ...

Страница 31: ...NCH 7F Block B High Tech Bldg 900 Yishan Road Shanghai 200233 CHINA Phone 86 21 5423 5577 FAX 86 21 5423 4677 EPSON HONG KONG LTD 20 F Harbour Centre 25 Harbour Road Wanchai Hong Kong Phone 852 2585 4600 FAX 852 2827 4346 Telex 65542 EPSCO HX SHENZHEN BRANCH 12F Dawning Mansion Keji South 12th Road Hi Tech Park Shenzhen 518057 CHINA Phone 86 755 2699 3828 FAX 86 755 2699 3838 EPSON TAIWAN TECHNOLO...

Страница 32: ...e Record X78A G 003 01 Revision 1 1 Issued September 6 2010 remove references to type 3 interface X78A G 003 01 Revision 1 0 Issued March 30 2007 minor edits updated schematics updated parts list added board layout X78A G 003 00 Revision 0 02 revised manual due to design changes added new schematics added new parts list X78A G 003 00 Revision 0 01 Initial draft of manual ...

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