Page 14
Epson Research and Development
Vancouver Design Center
S1D13513
S5U13513P00C100 Evaluation Board User Manual
X78A-G-003-01
Issue Date: 2010/09/06
Revision 1.1
CIOVDD1 is connected to 3.3V through a 0 ohm resistor, R70. If it is desired to have a
different voltage for CIOVDD1, R70 must be removed and the desired supply connected to
pin 15 of connector H6.
HVDD5 is always connected to 3.3V.
Note
The recommended range for HVDD1 (HIOVDD), HVDD2 (PIOVDD), HVDD3
CIOVDD2), and HVDD4 (CIOVDD1) is 3.0V~3.6V.
4.2 Clocks
S1D13513 has four clock inputs: BUSCLK, OSC1, OSC2 and CLKI3. BUSCLK and
CLKI3 require a clock provided by an external oscillator. OSC1 and OSC2 have an internal
oscillator and can work with a crystal or with an external oscillator.
For the S5U13513P00C100 evaluation board, OSC1 and OSC2 use crystals (10MHz for
OSC1 and 27MHz for OSC2).
For the S5U13513P00C100 evaluation board, CLKI3 is not used and is pulled to ground by
a 10k
Ω
resistor. However, if CLKI3 is required, connect a 14-pin, DIP package oscillator
in the Y1 footprint.
For the S5U13513P00C100 evaluation board, BUSCLK is not used and is pulled to ground
by a 10k
Ω
resistor. However, if BUSCLK is required, the BUSCLK pin is connected to the
H2 connector and to the P1 connector where it may be provided by the host development
platform.
4.3 Reset
The S5U13513P00C100 evaluation board can be reset using a push-button, or via an active
low reset signal from the host development platform (see H2 connector or P1 connector).
The reset signal will reset the S1D13513 Display Controller and is available on the H6 and
H7 connectors. It is possible to remove the reset signal from the H6 and H7 connectors by
removing the 0 Ohm resistor R80 from the board.
