15-2
Seiko Epson Corporation
S1C31D50 TECHNICAL MANUAL
(Rev. 1.00)
Figure 15.1.1 QSPI Configuration
15.2.
Input/Output Pins and External Connections
15.2.1.
List of Input/Output Pins
Table 15.2.1.1 lists the QSPI pins.
Table 15.2.1.1 List of QSPI Pins
Pin name
I/O
*
Initial status
*
Function
QSDIO
n
[3:0]
I or O
I (Hi-Z)
QSPI Ch.
n
data input/output pin
QSPICLK
n
I or O
I (Hi-Z)
QSPI Ch.
n
external clock input/output pin
#QSPISS
n
I or O
I (Hi-Z)
QSPI Ch.
n
slave select signal input/output pin
* Indicates the status when the pin is configured for the QSPI.
If the port is shared with the QSPI pin and other functions, the QSPI input/output function must be
assigned to the port before activating the QSPI. For more information, refer to the “I/O Ports” chapter.
15.2.2.
External Connections
The QSPI operates in master or slave mode. The memory mapped access mode is available only in
master mode. When QSPI Ch.
n
is operating in memory mapped access mode, the #QSPISS
n
output is
controlled by the internal state machine. In this case, only one external QSPI device can be connected.
When QSPI Ch.n is operating in register access master mode, the #QSPISS
n
output is directly controlled
by a register bit. In this case, GPIO pins other than #QSPISS
n
can also be used as the slave select output
ports to connect the QSPI to more than one external QSPI device.
Figures 15.2.2.1 to 15.2.2.7 show connection diagrams between the QSPI in each mode and external QSPI
devices.
Clock/shift
register
control
circuit
Pull-up/down
control circuit
I/O and slave
select control
circuit
Receive data
buffer
RXD[15:0]
Transmit data
buffer
TXD[15:0]
Interrupt
control
circuit
CPU core
Timer
1/2
CPOL
PUEN
DIR
MST
MSTSSO
TENDIE
RBFIE
TBEIE
TENDIF
OEIE
OEIF
RBFIF
TBEIF
DMA
controller
DMA
request
control
circuit
MODEN
BSY
Memory
mapped
access
control
circuit
TCSH[3:0]
RMADR[31:20]
DUMDL[3:0]
DUMLN[3:0]
DATTMOD[1:0]
DUMTMOD[1:0]
ADRTMOD[1:0]
ADRCYC
MMAEN
XIPACT[7:0]
XIPEXT[7:0]
MMABSY
SFTRST
CHDL[3:0]
CHLN[3:0]
TMOD[1:0]
LSBFST
CPHA
NOCLKDIV
Shift registers
FRLDMAENx
RBFDMAENx
TBEDMAENx
Clock
generator
16-bit timer
CLK_T16_
m
Underflow
Int
er
na
l dat
a b
us
CLK_QSPI
n
V
DD
Vcc
V
DD
V
DD
QSDIO
n
[3:0]
QSPICLK
n
#QSPISS
n
Содержание S1C31D50
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