Epson S1C17704, Техническое руководство

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19 SPI
19-6
EPSON
S1C17704 TECHNICAL MANUAL
PCLK
SPEN
SPI clock (master mode)
SPI_TXD register
Shift register
SPICLK pin
(CPOL = 0, CPHA = 1)
SPICLK pin
(CPOL = 0, CPHA = 0)
SDO pin
SPBSY
SPTBE
Interrupt
A
D7
B
D7
A
D6
A
D0
Write Write
Transmit buffer empty
Data A Data B
Figure 19.5.1 Data Transmit Timing Chart
Data receive control
In master mode, write dummy data to the SPI_TXD register (0x4322). Writing to the SPI_TXD register is used
as the trigger for data receiving as well as starting data transmission. Also actual data to be transmitted can be
written as the SPI module performs data transmission and reception simultaneously.
The SPI module starts output of the SPI clock from the SPICLK pin.
In slave mode, the SPI module waits for clock input from the SPICLK pin. When receiving data in slave
mode without any data transmission, it is not necessary to write data to the SPI_TXD register. The receive
process activates by the clock input from the master device. When performing data transmission and reception
simultaneously, the transmit data should be written to the SPI_TXD register before a clock is input.
The data bits are fetched in the shift register one by one at the rising or falling edge of the clock configured
with CPHA (D3/SPI_CTL register) and CPOL (D2/SPI_CTL register) (see Figure 19.4.1). The MSB of data is
received first.
When eight data bits are received in the shift register, the received data is loaded into the receive data buffer.
The received data in the buffer can be read from the SPI_RXD register (0x4324).
∗
SPI_RXD : SPI Receive Data Register (0x4324)
The SPI module provides the SPRBF flag (D1/SPI_ST register) for data receive control.
∗
SPRBF : Receive Data Buffer Full Flag in the SPI Status (SPI_ST) Register (D1/0x4320)
The SPRBF flag indicates the receive data buffer status; it goes 1 when the data received in the shift register
is loaded to the receive data buffer to indicate that the receive data can be read and returns to 0 when the
data in the receive data buffer is read out from the SPI_RXD register. An interrupt can be generated when
this flag goes 1 (see Section 19.6). Use this interrupt or read the SPRBF flag to check that the receive data
buffer contains valid data when reading received data. Although the receive data buffer size is one byte, the
previous received data can be maintained while the next data is being received as the shift register is separately
provided. However, be sure to read the receive data before the next data has been received. If the next data is
received before the previous received data in the receive data buffer has been read, the previous received data is
overwritten with the new data.
In master mode, the SPBSY flag that indicates the shift register status can be used as in data transmission.