Warning!
It is possible to mount the XU1 SoC module the wrong way round on the base board - always
check that the mounting holes on the base board are aligned with the mounting holes of the
XU1 SoC module.
The base board and module may be damaged if the module is mounted the wrong way round and
powered up.
1.1.6
Electrostatic Discharge
Electronic boards are sensitive to electrostatic discharge (ESD). Please ensure that the product is handled
with care and only in an ESD-protected environment.
1.1.7
Electromagnetic Compatibility
The XU1 SoC module is a Class A product and is not intended for use in domestic environments.
The product may cause electromagnetic interference, for which appropriate measures must be taken.
1.2
Features
•
Xilinx Zynq® Ult™ MPSoC
•
XCZU6CG/XCZU6EG/XCZU9EG/XCZU15EG device
•
FFVC900 package
•
Dual-/Quad-core ARM® Cortex™-A53 MPCore™ up to 1.5 GHz
•
Dual-core ARM® Cortex™-R5 MPCore™ up to 600 MHz
•
Mali-400 MP2 GPU (not for CG variants)
•
Xilinx 16nm FPGA fabric
•
294 user I/Os
•
14 ARM peripheral I/Os (SPI, SDIO, CAN, I2C, UART)
•
200 FPGA I/Os (single-ended, differential or analog)
•
152 HP I/Os (up to 1.8 V)
•
148 I/Os up to 1.8 V
•
4 I/Os up to 3.3 V (routed via level shifters)
•
48 HD I/Os (up to 3.3 V)
•
80 MGT signals (clock and data)
•
60 GTH MGT signals
•
20 GTR MGT signals
•
Speedgrade 1 devices
: 12 GTH MGTs @ 12.5 Gbit/sec and 6 reference input clock differential pairs
•
Other devices
: 12 GTH MGTs @ 15 Gbit/sec and 6 reference input clock differential pairs
•
4 GTR MGTs @ 6 Gbit/sec and 2 reference input clock differential pairs
•
PCIe Gen2
×
4 (Xilinx built-in PCIe hard block using GTR lines)
•
Up to 4 GB DDR4 SDRAM with ECC
•
64 MB quad SPI flash
•
16 GB eMMC flash
•
2
×
Gigabit Ethernet PHY (one PHY shared with one of the USB PHYs)
•
2
×
USB 2.0 PHYs
•
PHY0 configured as host or device
•
PHY1 configured as host (shared with one of the Gigabit Ethernet PHYs)
•
USB 3.0 (Xilinx built-in USB 3.0 hard block using GTR lines)
•
Real-time clock
D-0000-428-001
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Version 13, 15.08.2019
