Enclustra ME-XU1-15EG-1E-D12E-G1, Руководство пользователя

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Voltage Voltage Rated Voltage Shut down Influences
Supply Name Value Current Source via PWR_EN PWR_GOOD
VCC_INT 0.72 V
10
/0.85 V/0.9 V
(PL core supply)
35 A
11
VCC_MOD Yes Yes
VCC_PSINT 0.85 V/0.9 V
(PS core supply) 6 A
11
VCC_MOD Yes Yes
VCC_0V85
12
0.85 V
(GTR transceiver supply) 0.5 A VCC_1V2 Yes No
VCC_0V9 0.9 V 6 A
13
VCC_MOD
13
Yes Yes
VCC_1V2 1.2 V 6 A
14
VCC_MOD
14
Yes Yes
VCC_BAT_FPGA
15
1.2 V 10 mA VCC_BAT No No
VCC_1V8 1.8 V 3 A
16
VCC_MOD
16
Yes Yes
VCC_2V5 2.5 V 0.5 A VCC_3V3 Yes
17
No
VCC_3V3 3.3 V 6 A
18
VCC_MOD No Yes
VCC_5V0 5.0 V 0.15 A VCC_MOD No No
Table 14: Generated Power Supplies
11 12 13 14 15 16 17 18
In the standard configuration the PL core supply is 0.85 V. For configurations, in which a speedgrade -3E
MPSoC device is equipped, an assembly option is available to switch the PL core operating voltage to 0.9 V.
Similarly, in situations in which a speedgrade -2LE or -1LI device is used, an assembly option is available to
switch the PL core operating voltage to 0.72 V.
In the standard configuration the PS core supply is 0.85 V. For configurations, in which a speedgrade -3E
MPSoC device is equipped, an assembly option is available to switch the PS core operating voltage to 0.9 V.
PS and PL operation at 0.9 V is not supported on modules revision 1 and 2 - please refer to the
XU1 SoC Module Known Issues and Changes document [7] for details.
Please refer to the Enclustra Module Pin Connection Guidelines for general rules on the power pins [11].
Power Converter Synchronization
Starting with revision 3 modules, all switching converters used on the XU1 SoC module support
synchronization of the switching frequency with an external clock. The module includes a power synchro-
10
Support for 0.72 V core voltage has been added starting with revision 3.
11
On modules revision 1 and 2 the PL and PS core supplies were combined in a single power rail rated 20 A.
12
Starting with revision 3 modules, an LDO is used to generate the GTR transceiver supply, when a -1LI, -2LE, or -3E speedgrade
MPSoC device is used. For the other speedgrades, VCC_INT is used.
13
On modules revision 1 and 2 the VCC_0V9 supply is rated 2 A and is using VCC_3V3 as input.
14
On modules revision 1 and 2 the 1.2 V supply required for the MPSoC device, DDR components and Gigabit Ethernet PHYs is
separated into two separate power rails VCC_1V2 and VCC_1V2M both rated 2 A and using VCC_3V3 as voltage input.
15
Starting with revision 2 modules, a 1.2 V LDO is used to generate the battery voltage for the built-in RTC.
16
On modules revision 1 and 2 the VCC_1V8 supply is rated 2 A and is using VCC_3V3 as input.
17
On revision 1 modules, the 2.5 V converter cannot be disabled via PWR_EN signal.
18
On modules revision 1 and 2 the VCC_3V3 supply is rated 9 A.
D-0000-428-001 31 / 66 Version 13, 15.08.2019