2.9.8
Analog Inputs
The Zynq Ult MPSoC devices contain a system monitor in the PL and an additional system monitor
block in the PS. These are used to sample analog inputs and to collect information on the internal voltages
and temperatures.
The system monitor block in the PL provides a 10-bit ADC, which supports up to 17 external analog lines (1
dedicated differential input, 16 auxiliary differential inputs). The auxiliary analog lines of the MPSoC device
are available on the module connector; these I/Os have the abbreviation “AD” followed by the ADC channel
in the signal name. The ADC lines are always used differentially; for single-ended applications, the *_N line
must be connected to GND. The dedicated channel is not available on the module connector.
The analog input signals can be connected to any normal I/O FPGA bank, provided that all analog pins
belong to the same bank. Note that the HD I/O banks have a limited number of analog inputs and they
must be connected directly to the SYSMONE4 primitive instead of to the Xilinx System Management Wizard
IP core.
For detailed information on the ADC and system monitor, refer to the UltraScale Architecture System Monitor
document [20], Zynq Ult MPSoC Technical Reference Manual [19] and System Management Wizard
Product Guide [22].
Table 12 presents the ADC Parameters for the PL System Monitor. The PS System Monitor is only used for
monitoring the on-chip power supply voltages and die temperature.
Parameter
Value (PL Sysmon)
VCC_ADC
1.8 V
VREF_ADC
Internal
ADC Range
0-1 V
Sampling Rate per ADC
0.2 MSPS
Total number of channels available on the module connector
16 (only auxiliary inputs)
Table 12: System Monitor (PL) Parameters
2.10
Multi-Gigabit Transceiver (MGT)
There are two types of multi-gigabit transceivers available on the XU1 SoC module: GTH transceivers
(connected to the PL) and GTR transceivers (connected to the PS).
GTH Transceivers
There are 12 GTH MGTs available on the XU1 SoC module organized in three FPGA banks - Table
13 describes the connections.
The naming convention for the GTH MGT I/Os is:
MGT_B<BANK>_<FUNCTION>_<PACKAGE_PIN>_<POLARITY>.
For example, MGT_B228_TX2_M5_N is located on pin M5 of MGT I/O bank 228, it is a transmit pin and it has
negative polarity.
Starting with revision 3 modules, 4 additional GTH transceivers and 2 differential clock pairs may be routed
to the module connector, by using the “G1” assembly variants. Please refer to Section 2.9.2 for details on
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