User Manual
Section 5
GFK-2958L
May 2021
Detailed Description of I/O Modules
206
5.16
Digital Output Module EP-5111
Figure 106: Counter Module EP-5111
Figure 107: Connection Diagram EP-5111
With reference to the Connection Diagram (Figure 90):
1.
Track A
2.
Track B
3.
Cycle
4.
Direction 0/1 (24 V)
•
One 32-bit counter (AB) invertible, 24Vdc
•
Counting frequency 100 kHz max (AB 1/2/4-times sampling or pulse and
direction)
•
Latch value, comparison value, setting value, input filter (parametrizable)
•
HW gate reset, digital output for comparison
•
Alarm and diagnostic function with
μ
s time stamp
•
μ
s time stamp for counting value (for example, for speed measurements)
The counter module EP-5111 can read one square-wave signal (1 channel) (for example,
from an incremental encoder) with a maximum input frequency of 100 kHz. The 32-bit
counter can count up/down within a predetermined range of values.
The counter can be controlled using software or externally through the latch, gate, and reset
inputs. A digital output can be parameterized to be activated immediately upon either
dropping below, meeting, or exceeding the set comparison value. An overrun time can be
provided with the parameter Pulse duration. Thus, the PLC will recognize even signals
succeeding extremely fast.
