to the /RESET pin of a HC12/HCS12 MCU should never include a
large capacitance!
Clock Generation and PLL
The on-chip oscillator of the MC9S12DP512 can generate the
primary clock (OSCCLK) using a quartz crystal (Q1) connected
between the EXTAL and XTAL pins. The allowed frequency range is
0.5 to 16MHz. As usual, two load capacitors are part of the oscillator
circuit (C1, C2). However, this circuit is modified compared to the
standard Pierce oscillator that was used for the HC11 or most HC12
derivatives.
The MC9S12DP512 uses a Colpitts oscillator with translated
ground scheme. The main advantage is a very low current consumption,
though the component selection is more critical. The S12compact
circuit uses a 16MHz automotive quartz from NDK together with two
load capacitors of only 3.9pF. Furthermore, special care was taken for
the PCB design to introduce as little stray capacitance as possible in
respect to XTAL and EXTAL.
With an OSCCLK of 16MHz, the internal bus speed (ECLK)
becomes 8MHz by default. To realize higher bus clock rates, the PLL
has to be engaged. The MC9S12DP512 can be operated with a bus
speed of up to 25MHz, though most designs use 24MHz because this
value is a better basis to generate a wide range of SCI baud rates.
A passive external loop filter must be placed on the XFC pin. The
filter (R3, C3, C4) is a second-order, low-pass filter to eliminate the
VCO input ripple. The value of the external filter network and the
reference frequency determines the speed of the corrections and the
stability of the PLL. If PLL usage is not required, the XFC pin must be
tied to VDDPLL.
The choice of filter component values is always a compromise over
lock time and stability of the loop. 5 to 10kHz loop bandwidth and a
damping factor of 0.9 are a good starting point for the calculations.
With a quartz frequency of 16MHz and a desired bus clock of 24MHz, a
possible choice is R3 = 4.7k and C3 = 22nF. C4 should be
S12compact
14
