-11-
THEORY OF OPERATION
A block diagram of the M-1006K is shown in Figure 1. Operation centers around a custom LSI chip. This chip
contains a dual slope A/D (analog to digital) converter, display latches, seven segment decoder and display
drivers. A block diagram of the IC functions is shown in Figure 2. The input voltage or current signals are
conditioned by the selector switches to produce an output DC voltage with a magnitude between 0 and 199mV.
If the input signal is 100VDC, it is reduced to 100mVDC by selecting a 1000:1 divider. Should the input be
100VAC, it is first rectified and then divided down to 100mVDC. If current is to be read, it is converted to a DC
voltage by internal shunt resistors.
Figure 1
Input
Selector
Switches
AC
Converter
Ohms
Converter
Current
Shunt
V
V
Ω
I
Voltage
Divider
Selector
Switches
V
A/D
Converter
& Display
Driver
Display
Decimal
Point
DC
Analog
Data
For resistance measurements, an internal voltage source drives the test resistor in series with a known resistor.
The ratio of the test resistor voltage to the known resistor voltage is used to determine the value of the test
resistor.
The input of the 7106 IC is fed to an A/D converter. Here the DC voltage is changed to a digital format. The
resulting signals are processed in the decoders to light the appropriate LCD segments.
Timing for the overall operation of the A/D converter is derived from an external oscillator whose frequency is
selected to be 25kHz. In the IC, this frequency is divided by four before it clocks the decade counters. It is then
further divided to form the three convert-cycles phases. The final readout is clocked at about two readings per
second.
The digitized measurements are presented to the display as four decoded digits (seven segments) plus polarity.
The decimal point position on the display is determined by the selector switch setting.
A/D CONVERTER
A simplified circuit diagram of the analog portion of the A/D converter is shown in Figure 3. Each of the switches
shown represent analog gates which are operated by the digital section of the A/D converter. The basic timing
for switch operation is keyed by the external oscillator. The conversion process is continuously repeated. A
complete cycle is shown in Figure 3.
Any given measurement cycle performed by the A/D converter can be divided into three consecutive time
periods, autozero (AZ), integrate (INTEG) and read. A counter determines the length of the time periods. The
integrate period is fixed at 1,000 clock pulses. The read period is a variable time that is proportional to the
unknown input voltage. It can vary from zero counts for zero input voltage to 2,000 counts for a full scale input
voltage. The autozero period varies from 1,000 to 3,000 counts. For an input voltage less than full scale
autozero gets the unused portion of the read period. The value of the voltage is determined by counting the
number of clock pulses that occur during the read period.
During autozero a ground reference is applied as an input to the A/D converter. Under ideal conditions, the
output of the comparator would also go to zero. However, input-offset-voltage errors accumulate in the amplifier
loop and appear at the comparator output as an error voltage. This error is impressed across the AZ capacitor
where it is stored for the remainder of the measurement cycle. The stored level is used to provide offset voltage
correction during the integrate and read periods.
Содержание M-1006K
Страница 19: ...18 SCHEMATIC DIAGRAM...
