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Camera Link PCI Express (PCIe) Gen1 Framegrabbers

Appendix B: Board Diagrams

EDT, Inc.

2012 March 16

Appendix B: Board Diagrams

This section shows diagrams and key features for the various Camera Link PCIe boards.

Standard and Fiberoptic (FOX) Framegrabbers – PCIe “DVa”-series

PCIe8 DVa C-Link

PCIe4 DVa C-Link

PCIe8 DVa C-Link

1
3
5
7
9

2
4
6
8
10

Berg
connector

Optional Lemo

Base 0 /
primary

Base 1 /
secondary

Connectors

FVAL
LVAL
DVAL
PCLK

DEBUG

3 2 1

5 3 1

NORM
NORM

PROT
ALT

6 4 2

PoCL

Disabled

Enabled

3 2 1

FPGA boot select

Program-
mable

Protected

(sector 0)

(sector 3)

PoCL
select

LEDs

3 2 1

CAUTION!

To avoid a short, indicated by a red

LED near the connector, never plug a non-PoCL
cable or device into a PoCL-enabled EDT board.

= pin
= hole
= ground (pin)
= ground (hole)

Not to scale;

bold

= default.

slot for optional memory

PCIe8 DVa C-Link

1
3
5
7
9

2
4
6
8
10

Berg
connector

Optional Lemo

Base 0 /
primary

Base 1 /
secondary

Connectors

FVAL
LVAL
DVAL
PCLK

DEBUG

3 2 1

5 3 1

NORM
NORM

PROT
ALT

6 4 2

PoCL

Disabled

Enabled

3 2 1

FPGA boot select

Program-
mable

Protected

(sector 0)

(sector 3)

PoCL
select

LEDs

3 2 1

CAUTION!

To avoid a short, indicated by a red

LED near the connector, never plug a non-PoCL
cable or device into a PoCL-enabled EDT board.

= pin
= hole
= ground (pin)
= ground (hole)

Not to scale;

bold

= default.

slot for optional memory

PCIe4 DVa C-Link

1
3
5
7
9

2
4
6
8
10

Berg
connector

Optional Lemo

Base 0 /
primary

Base 1 /
secondary

Connectors

FVAL
LVAL
DVAL
PCLK

DEBUG

3 2 1

5 3 1

NORM
NORM

PROT
ALT

6 4 2

PoCL
select

LEDs
(on back)

3 2 1

= pin
= hole
= ground (pin)
= ground (hole)

Not to scale;

bold

= default.

slot for optional memory

PoCL

Disabled

Enabled

3 2 1

FPGA boot select

Program-
mable

Protected

(sector 0)

(sector 3)

CAUTION!

To avoid a short, indicated by a red

LED near the connector, never plug a non-PoCL
cable or device into a PoCL-enabled EDT board.

PCIe4 DVa C-Link

1
3
5
7
9

2
4
6
8
10

Berg
connector

Optional Lemo

Base 0 /
primary

Base 1 /
secondary

Connectors

FVAL
LVAL
DVAL
PCLK

DEBUG

3 2 1

5 3 1

NORM
NORM

PROT
ALT

6 4 2

PoCL
select

LEDs
(on back)

3 2 1

= pin
= hole
= ground (pin)
= ground (hole)

Not to scale;

bold

= default.

slot for optional memory

PoCL

Disabled

Enabled

3 2 1

FPGA boot select

Program-
mable

Protected

(sector 0)

(sector 3)

CAUTION!

To avoid a short, indicated by a red

LED near the connector, never plug a non-PoCL
cable or device into a PoCL-enabled EDT board.

Содержание PCIe Gen1 Framegrabbers

Страница 1: ...User s Guide Camera Link PCI Express PCIe Gen1 Framegrabbers High speed image capture for Camera Link on PCIe platforms Doc 008 04053 00 Rev 2012 March 16...

Страница 2: ...ved including interference that may cause undesired operation This equipment has been tested and found to comply with the limits for a Class A digital device pursuant to part 15 of FCC Rules These lim...

Страница 3: ...f business profits or information and the like arising out of the use or inability to use the Products even if Seller has been advised of the possibility of such damages Because some jurisdictions do...

Страница 4: ...plications 10 pciload 10 initcam 10 take 11 simple_take 11 simplest_take 12 simple_sequence 12 simple_irig2 12 serial_cmd 12 dvinfo 13 Triggering 13 Freerun Continuous 14 Triggered by EDT Board 14 Pul...

Страница 5: ...ink 28 Additional External Inputs 29 Via Berg Connector or Optional Lemo Connector 29 Via Optional Cable Assembly 30 Via Ribbon Cabling and D9 Connectors 31 Appendix C Timestamping 32 Camera Configura...

Страница 6: ...ulation of Camera Link image data EDT fiber extenders Example RCX C Link to extend Camera Link 100 kilometers over fiber EDT coax extenders Example RCX C Link Coax2 to extend Camera Link 600 feet over...

Страница 7: ...ct Datasheets and user s guides www edt com find product page User s guide legacy digital imaging products PCI products AIA products Product Documentation User s guide camera configuration setup Camer...

Страница 8: ...the software was built with or recompile relink the application with the latest package see Related Resources on page 2 Table 1 Requirements for I O bus type throughput cabling Product name Input outp...

Страница 9: ...igital imaging library and if necessary from the EDT DMA library routines in both libraries are documented in the EDT API The EDT digital imaging library provides a C language interface to your Camera...

Страница 10: ...ng mode 1 Double click the PdvShow desktop icon 2 Execute Camera Setup 3 In dialog box select your camera model 4 Click OK Use the initcam utility At a command prompt enter initcam f camera_config fil...

Страница 11: ...and the pdv_flshow subdirectory of the main distribution directory by default opt EDTpdv The command line invocation allows you to specify options for example pdvshow pdvU_C where U is the unit number...

Страница 12: ...ct subfolder For details see the README file in the pdvshow subfolder of the main distribution folder by default C EDT Pdv NOTE The pdvshow executable comes already built on Windows distributions so y...

Страница 13: ...on with 0 being the connector closest to the PCIe bus If you install one board in your host system the system will assign the default unit number 0 to that board If you install multiple boards the sys...

Страница 14: ...model and your operating mode Additional directives especially serial_baud serial_init serial_binit and other serial_ directives can be used to send serial commands when the system is initialized The...

Страница 15: ...se applications are the easiest to understand The most commonly useful options for these programs are described below Placeholders shown in italics should be replaced with your own values For a comple...

Страница 16: ...mbufs The number of ring buffers default is 1 A ring buffer is a portion of host memory preallocated for DMA and used in round robin fashion A setting of four optimizes pipelining one ring buffer curr...

Страница 17: ...quence Like simple_take but instead of capturing and saving one file at a time it captures a finite number of images limited to available memory into memory and then writes them all out at once See si...

Страница 18: ...m or pdvshow 3 Make sure no other PDV applications such as pdvshow are running 4 Run dvinfo One useful option is u unit The unit number if multiple boards are installed default is 0 first board Trigge...

Страница 19: ...eriod in the software for a large enough value to avoid timeouts If application blocking is acceptable configure the user_timeout period in the software for an infinite period user_timeout 0 to ensure...

Страница 20: ...l lasting at least 10 microseconds to these pins which in turn send a signal of the appropriate level to the camera trigger line typically CC1 The trigger cable can drive either pin high with respect...

Страница 21: ...config yourCamera cfg replacing yourCamera with the appropriate configuration file name for your camera and application NOTE For general testing use one of the genericXXcl cfg files provided with your...

Страница 22: ...ck the Pdv Utilities icon to bring up a command shell in the installation directory EDT Pdv For Linux Mac OS pciload is an application in opt EDTpdv To see currently installed and recognized EDT board...

Страница 23: ...ove the new firmware file to the directory in which you installed the EDT software 2 Power down the host and board 3 To avoid later confusion remove any other EDT boards from the host Table 3 Argument...

Страница 24: ...irmware in the flash memory in this case the date and revision number that shipped as of your purchase date If no errors are reported you have successfully booted from the protected sector 8 With the...

Страница 25: ...ckage with no arguments You should see information on each EDT board that can be seen If a board is not seen by the system Try uninstalling and reinstalling the EDT package and remember to reboot afte...

Страница 26: ...les Similarly do not remove files by hand Instead use the Add or Remove Programs facility in the Windows control panel Linux Try any of the following Failure during installation may be due to system p...

Страница 27: ...r example an EDT x8 board requires a slot that is x8 or x16 while an EDT x4 board requires a slot that is x4 x8 or x16 Also note that some motherboards will split lanes between two slots so that two x...

Страница 28: ...y connected and usable lanes at least four lanes for the 4 lane boards and at least eight lanes for the 8 lane boards Note that the legacy PCIe4 DV C Link has a maximum bandwidth of about 200 MB s due...

Страница 29: ...and message handling for EDT software libraries and can be helpful for debugging your programs See the EDT Message Handler Library in the API for specific routines and usage Before calling for techni...

Страница 30: ...Xclk Yclk Yclk 6 21 X3 Y3 Y3 19 8 X3 Y3 Y3 7 20 SerTC unused 100 ohms 20 7 SerTC unused terminated 8 19 SerTFG unused Z0 21 6 SerTFG unused Z0 9 18 CC1 unused Z1 22 5 CC1 unused Z1 10 17 CC2 unused Z...

Страница 31: ...3 PoCL select LEDs 3 2 1 CAUTION To avoid a short indicated by a red LED near the connector never plug a non PoCL cable or device into a PoCL enabled EDT board pin hole ground pin ground hole Not to s...

Страница 32: ...ted 1 2 1 2 sector 0 sector 3 LEDs on back NOTE Each transceiver up to 4 has its own LED which is steady green if that transceiver is getting a valid signal Transceiver 1 Transceiver 0 Transceiver 3 T...

Страница 33: ...y Base 1 secondary Connectors PCIe8 DV C Link Optional Lemo Not to scale bold default PCLK FVAL DVAL LVAL Base 1 secondary Base 0 primary Triggering external TTL 1 Maximum of lanes usually this jumper...

Страница 34: ...Link Legacy PCIe8 DV C Link 1 Trigger 0 Trigger 0 Trigger 0 2 Trigger 0 Trigger 0 Trigger 0 3 Trigger 1 Trigger 1 Trigger 1 4 Trigger 1 Trigger 1 Trigger 1 5 IRIG B IRIG B IRIG B 6 3 3V Reserved Reser...

Страница 35: ...estamping or both EDT p n 016 13840 June 2010 color Lemo D9 Function BNC BNC Label green 1 2 trigger 1 center conductor TRIG 1 red 2 9 reserved orange 3 7 trigger 0 center conductor TRIG 0 brown 4 8 t...

Страница 36: ...Triggering external TTL Any EDT framegrabber Generic representation of an EDT framegrabber Not to scale Trigger pins board dependent see individual board diagrams Secondary Primary Connectors Transce...

Страница 37: ...s For information on cable connectors and pinouts see Additional External Inputs on page 29 Camera Configuration Directives To enable the IRIG timestamp add to a camera configuration file method_heade...

Страница 38: ...rig_ok 1 u_char pps_ok 1 u_char had_irig_error 1 u_char had_pps_error 1 status u_char reserved 3 double timestamp holds a 64 bit unix seconds time This must be filled in by software Irig2Record IRIG t...

Страница 39: ...oards require the DMA size to be a multiple of 8 bytes Therefore with or without the IRIG option enabled the image size must be a multiple of 8 bytes To automatically enable IRIG functionality you can...

Страница 40: ...the Lemo connector note this function requires a special cable from EDT void pdv_irig_set_slave PdvDev pdv_p int onoff To use the direct register access to the current time value to fill in an Irig2R...

Страница 41: ...the board take l 10 to acquire 10 images and store them in main memory until the program exits Display Applications Because VxWorks applications typically include hardware dependent code EDT s GUI app...

Страница 42: ...ser it does not grow automatically as it would in other operating systems To prevent namespace conflicts application functions should be declared static Global variables should not be used if they are...

Страница 43: ...g EDT Inc 2012 March 16 38 Revision Log Below is a history of modifications to this guide Date By Rev Pp Detail 20120316 PH RH 01 All Created this new guide for PCIe framegrabbers by moving all non PC...

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