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57
57
57
57
4
4
4
4.2.4
.2.4
.2.4
.2.4 NAND
NAND
NAND
NAND with
with
with
with edge
edge
edge
edge evaluation
evaluation
evaluation
evaluation
The output of a NAND with edge evaluation is only 1
at
at
at
at least
least
least
least one
one
one
one
input is 0 and
all
all
all
all
inputs were
1 during the last cycle.
The output is set to 1 for the duration of one cycle and must be reset to 0 at least for the
duration of the next cycle before it can be set to 1 again.
A block input that is not used (x) is assigned: x = 1.
Timing diagram of a NAND with edge evaluation
4
4
4
4.2.5
.2.5
.2.5
.2.5 OR
OR
OR
OR
1
0
0
1
1
1
0
1
0
1
1
0
1
1
1
1
1
0
0
1
1
1
0
1
1
1
1
1
0
1
1
1
1
1
0
Содержание xLogic
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Страница 102: ...100 100 100 100 B B B B Blocks Blocks Blocks Blocks...
Страница 105: ...103 103 103 103 G G G G M M M M status status status status...
Страница 106: ...104 104 104 104 H H H H AM AM AM AM value value value value...
Страница 164: ...162 162 162 162 If the Memory Read block had been triggered the Q1 of ELC 12 CPU will be set 1...
Страница 204: ...202 202 202 202 Step Step Step Step 6 6 6 6 Moving Moving Moving Moving...
Страница 226: ...224 224 224 224...