iii
CONTENTS
CHAPTER 1
INTRODUCTION
1
1.1
KEY FEATURES
1
1.2
MAINBOARD COMPONENTS
3
1.3
PCI LOCAL BUS SPECIAL FEATURES
4
CHAPTER 2
HARDWARE CONFIGURATION
5
2.1
JUMPER AND MEMORY BANK LOCATIONS
5
2.2
JP01 - CPU TYPE SELECTION
6
2.3
S0-S2, JP0 - CPU CLOCK SELECTION
6
2.4
CPU INSTALLATION
7
2.5
CACHE CONFIGURATION
7
2.5.1
UPGRADING CACHE
8
2.5.2
CACHE SIZE AND MEMORY LOCATIONS
8
2.5.3
CACHE CHIP SOCKETS AND JUMPER
LOCATIONS
9
2.5.4
JP7-JP9 - CACHE JUMPER SETTING
9
2.5.5
INSTALLING CACHE CHIPS
10
2.6
JP4 - CACHE INVALIDATION INPUT FOR CPU
10
2.7
JP5 - CPU PIPELINE MODE SELECTION
11
2.8
JP6 - CPU INTERNAL CACHE WRITE BACK/WRITE
THROUGH SELECTION
11
2.9
JP12 - VIDEO SELECTION
12
2.10
JP1 - DISCHARGE CMOS RAM
12
2.11
JP2, JP3 - EPROM TYPE SELECTION
13
2.12
JP18 - PARALLEL PORT IRQ SELECTION
13
2.13
JP22, JP23 - PARALLEL PORT SETTING AND ECP DMA
SELECTION
14
2.14
MEMORY INSTALLATION
14
2.14.1
INSTALLING SIMM
17
