System Installation
96M4281o User’s Manual
3-4
CPU FSB / Memory Frequency synchronization
Support different memory frequencies depending on the CPU front side bus and the
type of DDR2 SDRAM.
CPU FSB
Memory Frequency
667 MHz
400MHZ / 533 MHZ / 667 MHz
533 MHz
400 MHZ / 533 MHz
3.3
Clear CMOS Operation
The following table indicates how to enable/disable CMOS Clear Function hardware
circuit by putting jumpers at proper position.
Normal Clear
JP7
Function
1-2 Short
Normal Operation
Ì
2-3 Short
Clear CMOS contents
3.4
WDT Function
The working algorithm of the WDT function can be simply described as a counting
process. The Time-Out Interval can be set through software programming. The
availability of the time-out interval settings by software or hardware varies from
boards to boards.
BLUEBOARD allows users control WDT through dynamic software programming.
The WDT starts counting when it is activated. It sends out a signal to system reset,
when time-out interval ends. To prevent the time-out interval from running out, a
re-trigger signal will need to be sent before the counting reaches its end. This action
will restart the counting process. A well-written WDT program should keep the
counting process running under normal condition. WDT should never generate a
system reset unless the system runs into troubles.
1
2
3
1
2
3
