BIOS Setup Information
96M4281o User’s Manual
4-13
CAS Latency Time
This option controls the number of SCLKs between the time a read command is
sampled by the DRAMs and the time the GMCH samples correspondent data from
the DRAMs.
The choice: 3, 4, 5, 6, and Auto.
DRAM RAS# to CAS# Delay
This option controls the number of SCLKs (SDRAM Clock) from a row activate
command to a read or write command. If your system installs good quality of
SDRAM, you can set this option to “3 SCLKs” to obtain better memory performance.
Normally, the option will be set to Auto.
The choice: 2, 3, 4, 5, 6, and Auto.
DRAM RAS# Precharge
This option controls the number of SCLKs for RAS# precharge. If your system
installs good quality of SDRAM, you can set this option to “3 SCLKs” to obtain
better memory performance. It is set to auto normally.
The choice: 2, 3, 4, 5, 6, and Auto.
Precharge delay (tRAS)
The choice: 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, and Auto.
System Memory Frequency
Users are recommended to use Auto for memory frequency selection.
The choice: 533MHz, 667MHz, and Auto.
SLP_S4# Assertion Width
The choice: 4 to 5 Sec., 3to 4 Sec, 2 to 3 Sec., 1 to 2 Sec.
System BIOS Cacheable
Selecting Enabled allows caching of the system BIOS ROM at F0000h-FFFFFh,
resulting in better system performance. However, if any program writes to this
memory area, a system error may result.
The choice: Enabled, Disabled.
