DIGITAL-LOGIC AG
PCCP5 Manual V2.3
81
#define MR_VDP_PITCH_QD 0x28 // Pitch of Video Display Window in
// quad words (8 bytes = 1QD)
#define MR_VDP_WIN_XL_L 0x2A // Display Window X-Left low
#define MR_VDP_WIN_XL_H 0x2B // Display Window X-Left high
#define MR_VDP_WIN_XR_L 0x2C // Display Window X-Right low
#define MR_VDP_WIN_XR_H 0x2D // Display Window X-Right high
#define MR_VDP_WIN_YT_L 0x2E // Display Window Y-Top low
#define MR_VDP_WIN_YT_H 0x2F // Display Window Y-Top high
#define MR_VDP_WIN_YB_L 0x30 // Display Window Y-Bottom low
#define MR_VDP_WIN_YB_H 0x31 // Display Window Y-Bottom high
#define MR_VDP_ZOOM_X 0x32 // Video Display Horizontal Zoom factor
#define MR_VDP_ZOOM_Y 0x33 // Video Display Vertical Zoom factor
//------------------------------------------------------------------------
// Color key registers
//------------------------------------------------------------------------
#define MR_VDP_CKEY_CTRL 0x3C // Video Color Key Control
#define MR_VDP_CKEY_0 0x3F //sw Graphics Color Key Reg 0 (blue)
#define MR_VDP_CKEY_1 0x3E // Graphics Color Key Reg 1 (green)
#define MR_VDP_CKEY_2 0x3D //sw Graphics Color Key Reg 2 (red)
#define MR_VDP_CKEY_M0 0x42 //sw Graphics Color Key Mask Reg0(blue)
#define MR_VDP_CKEY_M1 0x41 // Graphics Color Key Mask Reg1 (green)
#define MR_VDP_CKEY_M2 0x40 //sw Graphics Color Key Mask Reg2 (red)
#define MR_CRT_SCAN_LO 0x43 // Current CRTC Refresh Scanline Line
// Read Counter lo 8 bits
#define MR_CRT_SCAN_HI 0x44 // Current CRTC Refresh Scanline Line
// Read Counter hi 4 bits
//-------------------------------------------------------------------------
// Multimedia capabilities register_1 definitions (MR00):
//-------------------------------------------------------------------------
#define MCAPS_PLAYBACK 0x01 // Play back available
#define MCAPS_CAPTURE 0x02 // Capture available
//-------------------------------------------------------------------------
// Bit definition of Video Input Control Register1 (MR_VIN_CTRL_1)
//-------------------------------------------------------------------------
#define VIC1_NONINTERLACE 0x01 // Interlaced video input
#define VIC1_GAMEFORMAT 0x02 // Game format (duplicate field) video
#define VIC1_YUV422 0x00 // Video Input is YUV
#define VIC1_RGB565 0x04 // RGB16 video input (0 is YUV)
#define VIC1_RGB555 0x0C // RGB15 video input
#define VIC1_FORMAT 0x0E // all format bits
#define VIC1_HSYNC_HI 0x10 // H-Sync Polarity : Hi asserted
#define VIC1_VSYNC_HI 0x20 // V-Sync Polarity : Hi asserted
#define VIC1_FLD_DT_INV 0x40 // Field detect polarity inverted
#define VIC1_FLD_DT_LDE 0x80 // Field detect method leading edge
//-------------------------------------------------------------------------
// Bit definition of Video Input Control Register2 (MR_VIN_CTRL_2)
//-------------------------------------------------------------------------
#define VIC2_START_GRAB 0x01 // 1:start grab, 0:stop grab
#define VIC2_SINGLE 0x02 // 1:single frame, 0:continuous
#define VIC2_FIELD_GRAB 0x04 // 1:field grab, 0:frame grab
#define VIC2_ODD_FIELD 0x08 // 1:odd field grab, 0:even filed grab
#define VIC2_SCALE_X 0x10 // 1:enable x_scaling, 0:full screen
#define VIC2_SCALE_Y 0x20 // 1:enable y_scaling, 0:full screen
#define VIC2_YSCALE_ES 0x40 // 1:y-scale even spaced, 0:normal
#define VIC2_YSCALE_OW 0x80 // y-scale overwrite, 0:as per prev bit
//-------------------------------------------------------------------------
// Bit definition of Video Input Control Register3 (MR_VIN_CTRL_3)
//-------------------------------------------------------------------------
#define VIC3_X_MIRRORED 0x01 // capture direction, 1:right to left,
// 0: left to right
Содержание MICROSPACE PCC-P5
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