DIGITAL-LOGIC MICROSPACE PCC-P5, Техническое руководство пользователя

Страница: 48 / 148

DIGITAL-LOGIC AG
PCCP5 Manual V2.3
48
I/O Ad-
dress Read/Write
Status Description
00A0h - 00A1h are reserved for the slave programmable interrupt controller. The bit
definitions are identical to those of addresses 0020h - 0021h except where indicated.
00A0h R / W Programmable interrupt controller 2
00A1h R / W Programmable interrupt controller 2 mask
bit 7 = 0 Reserved
bit 6 = 0 Enable hard disk interrupt
bit 5 = 0 Enable coprocessor execution interrupt
bit 4 = 0 Enable mouse interrupt
bits 3-2 = 0 Reserved
bit 1 = 0 Enable redirect cascade
bit 0 = 0 Enable real time clock interrupt
00C0h R / W DMA channel 4 memory address bytes 1 and 0 (low)
00C2h R / W DMA channel 4 transfer count bytes 1 and 0 (low)
00C4h R / W DMA channel 5 memory address bytes 1 and 0 (low)
00C6h R / W DMA channel 5 transfer count bytes 1 and 0 (low)
00C8h R / W DMA channel 6 memory address bytes 1 and 0 (low)
00CAh R / W DMA channel 6 transfer count bytes 1 and 0 (low)
00CCh R / W DMA channel 7 memory address bytes 1 and 0 (low)
00CEh R / W DMA channel 7 transfer count bytes 1 and 0 (low)
00D0h R Status register for DMA channels 4-7
bit 7 = 1 Channel 7 request
bit 6 = 1 Channel 6 request
bit 5 = 1 Channel 5 request
bit 4 = 1 Channel 4 request
bit 3 = 1 Terminal count on channel 7
bit 2 = 1 Terminal count on channel 6
bit 1 = 1 Terminal count on channel 5
bit 0 = 1 Terminal count on channel 4
00D0h W Command register for DMA channels 4-7
bit 7 = 0 DACK sense active low
1 DACK sense active high
bit 6 = 0 DREQ sense active low
1 DREQ sense active high
bit 5 = 0 Late write selection
1 Extended write selection
bit 4 = 0 Fixed Priority
1 Rotating Priority
bit 3 = 0 Normal Timing
1 Rotating Timing
bit 2 = 0 Enable controller
1 Disable controller
bit 1 = 0 Disable memory-to-memory transfer
1 Enable memory-to-memory transfer
bit 0 = Reserved
Continued...