Both the memory chips and the PS DDR bank are powered from the 1.35V supply. The
mid-point reference of 0.675V is created with a simple resistor divider and is available to
the Zynq as external reference.
For proper operation it is essential that the PS memory controller is configured properly.
Settings range from the actual memory flavor to the board trace delays. For your
convenience, the Eclypse Z7 Vivado board files are available on the
and automatically configure the Zynq Processing System IP core with
the correct parameters.
For best DDR3L performance, DRAM training is enabled for write leveling, read gate,
and read data eye options in the PS Configuration Tool in Xilinx tools. Training is done
dynamically by the controller to account for board delays, process variations and
thermal drift. Optimum starting values for the training process are the board delays
(propagation delays) for certain memory signals.
Board delays are specified for each of the byte groups. These parameters are board-
specific and were calculated from the PCB trace length reports. The DQS to CLK Delay
and Board Delay values are calculated specific to the Eclypse Z7 memory interface
PCB design.
For more details on memory controller operation, refer to the Xilinx
4. Quad-SPI Flash
The Eclypse Z7 features a Spansion S25FL128S 4-bit Quad-SPI serial NOR flash. The
key device attributes are:
•
Part number S25FL128S
•
16 MB of memory
•
1-bit, 2-bit, and 4-bit bus widths supported
•
General use clock speeds up to 100 MHz, translating to 400 Mbps in Quad-SPI mode
•
Zynq configuration clock speeds up to 94 MHz
•
Powered from 3.3V
The Flash memory is used to provide non-volatile code and data storage. It can be used
to initialize the PS and PL of the Zynq device with a Zynq Boot Image (also known as
BOOT.BIN) generated using Xilinx tools such as Petalinux or Xilinx SDK. For
information on booting the Eclypse Z7 with a Zynq Boot image, see section “2.2 Quad
SPI Boot
Mode”.
The Flash is also commonly used to store non-configuration data needed by the
application. If doing this from a bare-metal application, The flash memory can be freely
accessed using standalone libraries included with a Xilinx SDK BSP project. If doing this
from a Petalinux generated embedded Linux system, the Flash can be partitioned as
