Zynq APSoC Architecture
The Zynq APSoC is divided into two distinct subsystems: The Processing System (PS)
and the Programmable Logic (PL). The figure below shows an overview of the Zynq
APSoC architecture, with the PS colored light green and the PL in yellow. Note that the
PCIe Gen2 controller and Multi-gigabit transceivers are not available on the Zynq-7020
device.
The PL is nearly identical to a Xilinx 7-series Artix FPGA, except that it contains several
dedicated ports and buses that tightly couple it to the PS. The PL also does not contain
the same configuration hardware as a typical 7-series FPGA, and it must be configured
either directly by the processor or via the JTAG port.
The PS consists of many components, including the Application Processing Unit (APU,
which includes 2 Cortex-A9 processors), Advanced Microcontroller Bus Architecture
(AMBA) Interconnect, DDR3 Memory controller, and various peripheral controllers with
their inputs and outputs multiplexed to 54 dedicated pins (called Multiplexed I/O, or MIO
pins). Peripheral controllers that do not have their inputs and outputs connected to MIO
pins can instead route their I/O through the PL, via the Extended-MIO (EMIO) interface.
The peripheral controllers are connected to the processors as slaves via the AMBA
interconnect, and contain readable/writable control registers that are addressable in the
processors’ memory space. The programmable logic is also connected to the
interconnect as a slave, and designs can implement multiple cores in the FPGA fabric
that each also contain addressable control registers. Furthermore, cores implemented in
the PL can trigger interrupts to the processors and perform DMA accesses to DDR3
memory.
