on the desired frequencies and phase relationships specified by the user. The wizard
will then output an easy-to-use wrapper component around these clocking resources
that can be inserted into the user’s design. The clocking wizard can be accessed from
within the Vivado and IP Integrator tools.
Figure 5.1 outlines the clocking scheme used on the Eclypse Z7. Note that the
reference clock output from the Ethernet PHY is used as the 125 MHz reference clock
to the PL, in order to cut the cost of including a dedicated oscillator for this purpose.
Keep in mind that CLK125 will be disabled when the Ethernet PHY is held in hardware
reset by driving the PHYRSTB signal low.
Figure 5.1: Eclypse Z7 clocking.
6. Reset Sources
The Eclypse Z7 provides several different methods of resetting the Zynq-7000 device,
as described in the following sections:
6.1. Power-on Reset
The Zynq PS supports external power-on reset signals. The power-on reset is the
master reset of the entire chip. This signal resets every register in the device capable of
being reset. The Eclypse Z7 drives this signal from the VCC4V3 supply, the final non-
adjustable supply to be brought up in the power-on sequence, in order to hold the
system in reset until all power supplies are valid. A push-button, labeled BTNP, can be
used to toggle the power-on reset signal. BTNP is located on the underside of the
Eclypse Z7, below the SD card slot.
