Zynq Boot Image into a Flash device attached to the Zynq. Once the Quad SPI Flash
has been loaded with a Zynq Boot Image, the following steps can be followed to boot
from it:
1.
Attach a power supply to the Eclypse Z7 via the barrel jack (J11).
2.
Place a single jumper on JP5, shorting the two center pins (labeled
“QSPI”).
3.
Turn the board on by flipping the power switch to the ON position. The board will now
boot the image stored in the Quad SPI flash.
2.3. JTAG Boot Mode
When placed in JTAG boot mode, with the two leftmost pins of JP5 shorted (labeled
“JTAG”), the processor will wait until software is loaded by a host computer using the
Xilinx tools. After software has been loaded, it is possible to either let the software begin
executing, or step through it line by line using Xilinx SDK.
It is also possible to directly configure the PL over JTAG, independent of the processor.
This can be done using the Vivado Hardware Server.
The Eclypse Z7 is configured to boot in Cascaded JTAG mode, which allows the PS to
be accessed via the same JTAG port as the PL. It is also possible to boot the Eclypse
Z7 in Independent JTAG mode by shorting unloaded jumper JP3. This will cause the PS
to not be accessible from the onboard JTAG circuitry, and only the PL will be visible in
the scan chain. To access the PS over JTAG while in independent JTAG mode, users
will have to route the signals for the PJTAG peripheral over EMIO, and use an external
device to communicate with it.
3. DDR3L Memory
The Eclypse Z7 includes two Micron MT41K256M16TW-107 DDR3L memory
components creating a single rank, 32-bit wide interface and a total of 1 GiB (Gibi-byte,
or 1,073,741,824 bytes) of capacity. The DDR3L is connected to the hard memory
controller in the Processor Subsystem (PS), as outlined in the Zynq documentation.
Note
:
The Eclypse Z7 may alternatively use an ISSI IS43TR16256A(L)-125KBL DDR3L
memory. This part is compatible with the same timings as the Micron part.
The PS incorporates an AXI memory port interface, a DDR controller, the associated
PHY, and a dedicated I/O bank. DDR3L memory interface speeds up to 533 MHz/1066
MT/s are supported.
The Eclypse Z7 was routed with 40 ohm (+/-10%) trace impedance for single-ended
signals, and differential clock and strobes set to 80 ohms (+/-10%). A feature called DCI
(Digitally Controlled Impedance) is used to match the drive strength and termination
impedance of the PS pins to the trace impedance. On the memory side, each chip
calibrates its on-die termination and drive strength using a 240 ohm resistor on the ZQ
pin.
