DMM-16R-AT User Manual V1.31
www.diamondsystems.com
Page 25
Page 2 (extended page): Digital I/O Control and FIFO
Base + 10
Read
FIFO Depth bits 7 -0
Bit No.
7
6
5
4
3
2
1
0
Name
FD7
FD6
FD5
FD4
FD3
FD2
FD1
FD0
Base + 11
Read
FIFO Depth bit 8
Bit No.
7
6
5
4
3
2
1
0
Name
FD9
FD8
This 10-bit value indicates the current number of samples in the A/D FIFO, 0 to 512. This register is cleared to 0
when the FIFO is reset.
Base + 12
Read/Write
DIO port A (Enhanced mode)
Bit No.
7
6
5
4
3
2
1
0
Name
DIOA7
DIOA6
DIOA5
DIOA4
DIOA3
DIOA2
DIOA1
DIOA0
A7-0
Digital I/O port A data
When DIO Enhanced mode is selected, this register is used to read/write data to port A.
Alternate Functions (see Counter/Timer Operation Chapter)
A0
External A/D trigger
A2
Counter 0 Gate Input
Alternate functions are available only when port A is configured as input port (DIRA = 0).
Base + 13
Read/Write
DIO port B (Enhanced mode)
Bit No.
7
6
5
4
3
2
1
0
Name
DIOB7
DIOB6
DIOB5
DIOB4
DIOB3
DIOB2
DIOB1
DIOB0
B7-0
Digital I/O port B data
When DIO Enhanced mode is selected, this register is used to read/write data to port B.
When reading these two registers, the value of the corresponding FPGA pins is always returned. In input
mode, the pins are driven by the I/O connector. In output mode, the pins are driven by the values in these
registers.