DMM-16R-AT User Manual V1.31
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Page 20
Base + 10
Read
Counter/Timer and FIFO Status Register (pages 0 and 1 only)
Bit No.
7
6
5
4
3
2
1
0
Name
WAIT
PAGE
FIFOEN SCANEN CLKFRQ
OVF
HF
EF
WAIT
Analog input circuit status. Whenever register 2 (channel register) or 11 (input range register) is
written to, WAIT will go high for approximately 10 S as the circuit adjusts to the new signal.
1
The analog input circuit is busy settling on a new signal. Do not perform A/D conversions
when WAIT = 1.
0
The circuit is ready for A/D conversions
PAGE
Readback of PAGE bit described on previous page. If EXTPG = 0, then the PAGE bit reads back
the current page setting 0 or 1. If EXTPG = 1, then the FPGA is forced into page 2, and PAGE
reads back as 0. However its register contents are preserved, so that later when EXTPG returns
to 0 the page returns to its previous setting of 0 or 1.
FIFOEN
Readback of FIFOEN bit described on previous page
SCANEN
Readback of SCANEN bit described on previous page
CLKFRQ
Readback of CLKFRQ bit described on previous page
OVF
FIFO overflow flag; 0 = no overflow; 1 = overflow
Overflow is defined as the state when the FIFO is full and another A/D conversion occurs before
any data is read out of the FIFO. In an overflow condition the FIFO contents are preserved, and
no new data will be written to the FIFO. To clear an overflow condition, the FIFO must be reset
with the FIFORST bit in register 10.
HF
FIFO half full flag; 0 = FIFO is less than half full; 1 = FIFO is at least half full
EF
FIFO empty flag; 0 = FIFO is not empty; 1 = FIFO is empty
Additional FIFO flags OF (overflow) and UF (underflow are accessible in page 2.