Diamond Systems DMM-16R-AT, Руководство пользователя, Страница: 10 / 39

DMM-16R-AT User Manual V1.31
www.diamondsystems.com
Page 10
5. I/O REGISTER MAP
5.1 Overview
DMM-16R-AT occupies 16 bytes in I/O space. For ISA bus operation, these registers are located in the ISA
bus I/O address space. For PCI bus operation, these registers are located in the BAR0 configured during
system boot.
A functional list of these registers is provided below, and detailed bit definitions are provided on the next page
and the following chapter.
Base + Write Function Read Function
0 Start A/D conversion A/D LSB
1 D/A LSB A/D MSB
2 A/D channel register A/D channel register
3 Digital output port Digital input port
4 D/A 0 MSB Update D/A
5 D/A 1 MSB Update D/A
6 D/A 2 MSB Update D/A
7 D/A 3 MSB Update D/A
8 Clear interrupt flip flop Status register
9 Interrupt control register Interrupt control register readback
10 Ctr/Timer and FIFO Control Register FIFO / status register
11 Analog Configuration Register Analog and FIFO register readback
Addresses 12-15 form a window into two 4-byte pages. Addresses 10-15 constitutes the extended page of 6
bytes. The page is selected with bits in registers 8 and 10.
Page 0: 82C54 counter/timer
12 Counter/timer 0 data register Counter/timer 0 data register
13 Counter/timer 1 data register Counter/timer 1 data register
14 Counter/timer 2 data register Counter/timer 2 data register
15 Counter/timer control register Counter/timer control register
Page 1: Calibration Control
12 EEPROM / TrimDAC data register EEPROM / TrimDAC data register
13 EEPROM / TrimDAC address register EEPROM / TrimDAC address register
14 Calibration control register Calibration status register
15 EEPROM access key FPGA code version
Page 2 (extended page): Digital I/O Control and FIFO
10 FIFO Depth Register 7 -0
11 FIFO Depth Register 9 - 8
12 Port A output data Port A input data
13 Port B output data Port B input data
14 LED control LED and FIFO status
15 Port direction control Port direction control readback