DMM-16R-AT User Manual V1.31
www.diamondsystems.com
Page 16
Base + 4 through Base + 7
Write
DAC 0
– 3 MSB
Bit No.
7
6
5
4
3
2
1
0
Name
DA11
DA10
DA9
DA8
Definitions:
DA11
– 8 D/A data bits 11 – 8 for the selected channel. DA11 is the MSB.
Base + 4 is used for D/A 0, Base + 5 is used for D/A 1, Base + 6 is used for D/A 2, and Base + 7 is used for
D/A 3.
The final D/A value is constructed of the 4 upper bits written to these registers combined with the 8 lower bits
of the D/A value written to Base + 1. Writing data to any of these 4 registers causes these 4 bits and the 8
lower bits from Base + 1 to be transferred to the selected D/A channel. However the D/A is not updated until a
read operation is performed on one of these 4 addresses. This lets you write data to more than one D/A and
then update all of them at the same time.
Since the Base + 1 register is shared by all 4 D/A channels, each D/A channel must have its data written in
the proper sequence. First write the LSB to Base + 1, then write the MSB to one of the MSB registers 4-7
depending on the D/A selected. Repeat these two writes for each D/A you want to update. After all data is
written, read from any of these registers to update all the D/A channels simultaneously.
Note that even though all channels are updated simultaneously, a channel will only change if it has new data
written to it since the last update operation. Otherwise it will maintain its present value during the update
operation.
Base + 4 through Base + 7
Read
Update D/A channels / read FPGA ID and revision
Reading from any of these 4 addresses will cause the 4 analog outputs to be updated. All outputs are
updated simultaneously. See detailed description above.
Register 7 reads back the FPGA major ID for this design, 0x14.
Register 6 reads back the FPGA minor ID for this design, 0x01.
Register 5 reads back the FPGA revision. This starts with 0x01 and increments with each successive version
of the FPGA.
Registers 4 reads back as 0x00 always.