24
Chapter 5 Ports and Connectors
Chapter 5
BAT 2
1
Clear COMS (JP1)
M.2 2280 (M Key)
SATA 3.0
SATA 1
1
AMD
GX-217GI
GX-224IJ
GX-220IJ
D
D
R4_2
SOD
IMM
D
D
R4_1
SOD
IMM
CPU Fan
1
BAT 3
BAT 1
USB 3.0_1
1
4
Intrusion
Door 8
1
FPGA Program (J12)
MCU Program (J15)
1
1
SATA 3.0
SATA 0
1
5
1
8
Intrusion
Door 1~6
4
S/PDIF
1
6
1
7
12
2
1
Speaker
1
DC_out
5V/2A
COM 2
1
5
6
COM 1
1
5
6
DO 17~32
4
DO 1~16
9
1
10
9
1
10
18
18
10
1
11
20
10
1
11
20
DI 17~32
DI 1~16
iButton Intrusion
Door7
1
3
4
1
2
LPC
LAN 1
LAN 2
DC_in
USB 2.0_4
1
4
USB 2.0_3
1
4
USB 2.0_2
1
4
USB 2.0_1
1
4
USB 3.0_2
1
4
DP 0
DP 1
5.1CH
L
or
1
2
3
4
1
COM 3
3
6
4
5
10
COM 4/5
1
6
SPI
Flash
Power LED
HDD LED
Power Button
Reset Button
SRAM
USB 2.0_5
1
4
BAT 4
(J20)
1
®
SRAM
FPGA
Note: GX-217GI supports only one DIMM slot
1
Standby Power LED
BAT 2
1
Clear COMS (JP1)
M.2 2280 (M Key)
SATA 3.0
SATA 1
1
AMD
GX-217GI
GX-224IJ
GX-220IJ
D
D
R4_2
SOD
IMM
D
D
R4_1
SOD
IMM
CPU Fan
1
BAT 3
BAT 1
USB 3.0_1
1
4
Intrusion
Door 8
1
FPGA Program (J12)
MCU Program (J15)
1
1
SATA 3.0
SATA 0
1
5
1
8
Intrusion
Door 1~6
4
S/PDIF
1
6
1
7
12
2
1
Speaker
1
DC_out
5V/2A
COM 2
1
5
6
COM 1
1
5
6
DO 17~32
4
DO 1~16
9
1
10
9
1
10
18
18
10
1
11
20
10
1
11
20
DI 17~32
DI 1~16
iButton Intrusion
Door7
1
3
4
1
2
LPC
LAN 1
LAN 2
DC_in
USB 2.0_4
1
4
USB 2.0_3
1
4
USB 2.0_2
1
4
USB 2.0_1
1
4
USB 3.0_2
1
4
DP 0
DP 1
5.1CH
L
or
1
2
3
4
1
COM 3
3
6
4
5
10
COM 4/5
1
6
SPI
Flash
Power LED
HDD LED
Power Button
Reset Button
SRAM
USB 2.0_5
1
4
BAT 4
(J20)
1
®
SRAM
FPGA
Note: GX-217GI supports only one DIMM slot
1
Standby Power LED
LPC
1
2
13
14
LPC Connector
The Low Pin Count Interface was defined by Intel
®
Corporation to facilitate the industry’s transition
towards legacy free systems. It allows the integration of low-bandwidth legacy I/O components
within the system, which are typically provided by a Super I/O controller. Furthermore, it can be
used to interface firmware hubs, Trusted Platform Module (TPM) devices and embedded control
-
lers. Data transfer on the LPC bus is implemented over a 4 bit serialized data interface, which uses
a 24MHz LPC bus clock. For more information about LPC bus, please refer to the Intel
®
Low Pin
Count Interface Specification Revision 1.1’. The table above indicates the pin functions of the LPC
connector.
• BIOS Setting
Configure the LPC port's connection to a TPM module in the Advanced (“
Peripheral Configuration”
submenu) and the "Security" menus of the BIOS. Refer to Chapter 7 for more information.
Pin
Pin Assignment
Pin
Pin Assignment
1
L_CLK
2
L_AD1
3
L_RST#
4
L_AD0
5
L_FRAME#
6
3V3
7
L_AD3
8
GND
9
L_AD2
10
Key
11
INT_SERIRQ
12
GND
13
5VSB
14
5V
SATA (Serial ATA) Connectors
• 2 Serial ATA 3.0 ports
- SATA port 0 and 1 with data transfer rate up to 6Gb/s
•
Pin 7 pr5V power and can switch b5V and GND automatically
Features
The Serial ATA connectors are used to connect the Serial ATA device, i.e., a SATA DOM. For
SATA DOM that requires external power supply, there is a 5V DC-out connector. Please refer to
5V DC-out on the next page.
• BIOS Setting
Configure the Serial ATA drives in the Advanced menu (“SATA Configuration” submenu) of the
BIOS. Refer to Chapter 7 for more information.
SATA 1
SATA 0
7
RXN
GND
TXP
TXN
+5V / GND
1
RXP
GND
S
AT
A
3.0
6Gb/s