Denon DCD-A100, Руководство по обслуживанию

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61
(
※
1)
(
※
2)
When (68)pin is "L", version of FPGA side is acquired entering FPGA VER display mode.
60 VCC2 +3.3V_D
61 P3_0/A8(/-/D7) FL_CS O H FL Driver Chip Select
62 VSS GND
63 P2_7/AN2_7/A7(/D7/D6) DIR1_CIDO I DIR DATA OUT
64 P2_6/AN2_6/A6(/D6/D5) DIR1_CLK O L DIR CLOCK
65 P2_5/AN2_5/A5(/D5/D4) DIR1_CE O L DIR CHIP ENABLE
66 P2_4/AN2_4/A4(/D4/D3) DIR1_CODI O L DIR DATA IN
67 P2_3/AN2_3/A3(/D3/D2) BE_UART_OK I B/E UART communication beginning notification port
68 P2_2/AN2_2/A2(/D2/D1) FPGA Ver.CONT O H When Ver is acquired from FPGA, it makes it to "L".
69 P2_1/AN2_1/A1(/D1/D0) DSDMUTE I AMUTE signal from B/E
70 P2_0/AN2_0/A0(/D0/-) SACD_LED_IN I SACD_LED control signal judged from BE side
71 P1_7/D15/*INT5 P_CONT O L POWER ON/STANDBY control
72 P1_6/D14/*INT4 AMUTE_IN I AMUTE signal judged from BE side (H;Mute release)
73 P1_5/D13/*INT3 REMOTE I RC input signal INT3 specification.
74 P1_4/D12 1.2V CONT O H 1.2V regulator ON/OFF control for DV3.2 / MODE3_IN
75 P1_3/D11 FPGA_CI O L FPGA control
76 P1_2/D10 FPGA_C2 I L FPGA control
77 P1_1/D9 MUTE O H Mute signal for RELAY control (L:Mute release)
78 P1_0/D8 FPGA_C3 O L FPGA control
79 P0_7/AN0_7/D7 MUTE (RSV_2) I Compulsion MUTE from DV3.2
80 P0_6/AN0_6/D6 FPGA_C4 I FPGA control
81 P0_5/AN0_5/D5 AL32_EMPH O/(I) L FPGA emphasis selection port.
When DIR reception signal is EMPHASIS, "H"
82 P0_4/AN0_4/D4 OPEN O H DENON LINK ON/OFF control (L;ON H;OFF)
83 P0_3/AN0_3/D3 AL32_TEST5 O/(I) L FPGA FS selection port
84 P0_2/AN0_2/D2 AL32_TEST4 O/(I) H FPGA FS selection port
85 P0_1/AN0_1/D1 AL32_TEST3 O/(I) L FPGA FS selection port
86 P0_0/AN0_0/D0 AL32_SIGN_SEL O L FPGA output signal INT/EXT selection port
87 P10_7/AN7/*KI3 OPEN O L
[non] R672 100k
Ω
PU
88 P10_6/AN6/*KI2 OPEN I
[non] R673 100k
Ω
PU
89 P10_5/AN5/*KI1 KEY1 I BUTTON A/D input 1
90 P10_4/AN4/*KI0 KEY0 I BUTTON A/D input 0
91 P10_3/AN3 OPEN I [non]
92 P10_2/AN2 OPEN I [non]
93 P10_1/AN1 BE_PWR_MONI I DV3.2(BE) Power supply watch of +3.3V.
+3.0V or more is assumed to be "H"
(Distinguish by L
→
H, H
→
L, and 3.0V standard).
94 AVSS GND
95 P10_0/AN0 MODEL_ID1 I MODEL ID setting(1) Sets it by resistance PULL UP/DN.
(DCD-1650SE,DCD-2010AE ; L ,
DCD-1500SE,DCD-1510AE ; H)
96 VREF +3.3V_D
97 AVCC +3.3V_D
98 P9_7/*ADTRG/SIN4 OPEN O L [non]
99 P9_6/ANEX1/SOUT4 FL_DA O L FL Sirial Data Out
100 P9_5/ANEX0/CLK4 FL_CLK O L FL Sirial Clock Out
UNLOCK
32kHz
64kHz
128kHz
44.1kHz
48kHz
96kHz
192kHz
FS0 0 1 0 1
FS1 0 0 1 1
pin 91 83 84 85
bit 0 1 2 3
Pin No. Pin Name Signal Name I/O Initial Function