Denon DCD-A100, Руководство по обслуживанию

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60
M3062LFGPGP Terminal Function
Pin No. Pin Name Signal Name I/O Initial Function
1 P9_4/DA1/TB4IN BE_KEY0 I H B/E Button Signal 1 D/A Enable PU, PD is impossible
2 P9_3/DA0/TB3IN BE_KEY1 I H B/E Button Signal 2 D/A Enable PU, PD is impossible
3 P9_2/TB2IN/SOUT3 DAC_DATA_IN O L DAC CONTROL DATA INPUT PORT
4 P9_1/TB1IN/SIN3 DAC_CS_IN O H DAC CHIP SELECT PORT
5 P9_0/TB0IN/CLK3 DAC_CK_IN O L DAC CONTROL CLOCK PORT
6 BYTE BYTE I GND
7 CNVSS CNVSS I UP DATE Control terminal
8 P8_7/XCIN CONT1 I L [Reserve]
9 P8_6/XCOUT CONT2 I L [Reserve]
10 *RESET RESET I Reset input
11 XOUT XOUT O Main clock output
12 VSS GND
13 XIN XIN I Main clock output
14 VCC1 +3.3V_D
15 P8_5/*NMI NMI I [non] PU to 3.3V_D (R527 : 10k)
16 P8_4/*INT2/ZP BE_DAC_CS (MLEN1) I B/E DAC data reception start (end) confirmation port
17 P8_3/*INT1 DIR1_CFLUG I DIR data change detection port
18 P8_2/*INT0 P_DOWN I H It is power failure detection and Mute effective.
19 P8_1/TA4IN/*U BE_FL_CS I B/E FL data reception end confirmation port [outside
interruption]
20 P8_0/TA4OUT/U CONT3 I L [Reserve]
21 P7_7/TA3IN LED-ON O Power indicator "ON" control
22 P7_6/TA3OUT LED-STBY O Power indicator "OFF" control
23 P7_5/TA2IN/*W DF_RST(BE_DAC_RESET) I B/E DAC RESET port
24 P7_4/TA2OUT/W MODE2 I [Reserve] LED AL32 or MP3 44.1k/48k "L" 32k"H"
25 P7_3/*CTS2/*RTS2/TA1IN/*V VOLTAGE-PROTECT I H High VOLTAGE-Detect (JP only)
26 P7_2/CLK2/TA1OUT/V BE_FL_CK I B/E FL Data Serial Data Clock
27 P7_1/RXD2/SCL2/TA0IN/TB5IN BE_FL_DT I B/E FL Data Serial Data Input
28 P7_0/TXD2/SDA2/TA0OUT USB-SENS I L [Reserve]
29 P6_7/TXD1/SDA1 BE_UART_MOSI O For B/E UART Rx Data
30 P6_6/RXD1/SCL1 BE_UART_MISO I For B/E UART Rx Data
31 P6_5/CLK1 FS0 O L FS0/FS1 in combination, EXT IN FS type of signal output.
It uses it for the de-emphasis characteristic selection of
FPGA.
32 P6_4/*CTS1/*RTS1/*CTS0/CLKS1 FS1 O L
33 P6_3/TXD0/SDA0 28 TXD O L For USB UART DATA
34 P6_2/RXD0/SCL0 28 RXD I For USB UART DATA
35 P6_1/CLK0 BE_DAC_CK I B/E DAC Data Serial Data Clock
36 P6_0/*CTS0/*RTS0 INT 0 O L [Reserve]
37 P5_7/*RDY/CLKOUT BE_DAC_DT I L B/E DAC Data Serial Data Input
38 P5_6/ALE DIR1_AUDIO I AUDIO/non-AUDIO distinction
39 P5_5/*HOLD EPM O L UP DATE Control terminal
40 P5_4/*HLDA E2P_CLK O L EEPROM CLK / UP DATE Control terminal
41 P5_3/BCLK E2P_DO I EEPROM reading data / UP DATE Control terminal
42 P5_2/*RD E2P_DI O L EEPROM writing data / UP DATE Control terminal
43 P5_1/*WRH/*BHE E2P_CS O L EEPROM CE / UP DATE Control terminal
44 P5_0/*WRL/*WR CE O L UP DATE Control terminal
45 P4_7/*CS3 USB_RST O L USB RESET contlrol
46 P4_6/*CS2 LED_AL32 O L AL32 LED control
47 P4_5/*CS1 PWB CHECK I PWB board check mode switch 3 , PU R550 : 10k
48 P4_4/*CS0 PWB CHECK I PWB board check mode switch 2 , PU R549 : 10k
49 P4_3/A19 PWB CHECK I PWB board check mode switch 1 , PU R548 : 10k
50 P4_2/A18 PWB CHECK I PWB board check mode switch 0 , PU R547 : 10k
51 P4_1/A17 DIR1_ERROR I DIR1 ERROR distinction
52 P4_0/A16 DAC_CONT_SEL O L Whether SYSCON controls DAC or DV3.2 controls is
switched
53 P3_7/A15 DAC_RST_IN O L DAC RESET
54 P3_6/A14 FL_RST O L FL Driver Reset
55 P3_5/A13 REMOCON_OUT O L B/E Remocon Code output
56 P3_4/A12 BE_RST O L B/E Reset Signal
57 P3_3/A11 MODEL_ID2 I [Reserve]
58 P3_2/A10 DV_STB I B/E start-up confirmation port
59 P3_1/A9 DIR1_RST O L DIR1 RESET