Datron TW7201I, Руководство пользователя

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4: Theory of Operation
TW7201I-MS 4-3
4.2.1
Front Panel
Processor Board
The main function of the Front Panel Processor board is to process commands
and interact with the transceiver through the DHSL modem. It also provides
transmit and receive paths for front panel audio processing.
Front Panel
Connections The Front Panel Processor board connects directly to the microphone
connectors (J9, J10),
CLAR
control (J8),
PWR OFF/VOL
switch (J7), LCD
board (J3 and J4), Switch Matrix board and Keypad (J6) and DHSL Modem
board (J1).
Transmit Audio The Front Panel Processor board receives transmit audio from the front panel
microphone through connectors J9 or J10 pin 4. The transmit audio goes to the
voice operated gain adjusting device (VOGAD) U17 which also provides
speech compression. The transmit audio continues through switch Q7 and is
output to the DHSL Modem board through J1 pin 25 (PRMICA).
Receive Audio The Front Panel Processor board inputs receive audio from the DHSL Modem
board as squelch audio (SQA) through J1 pin 30. It then goes to the top of
volume control (J7 pin 3) and returns through the volume wiper (J7 pin 4).
The receive audio goes to the audio amplifier U14 that amplifies the audio
signal and outputs it to the speaker through J5. Switching relay K1 connects
the receive audio to the speaker. The receive audio is also routed to
microphone jacks J9 and J10 pin 2.
External Speaker
and Alarm External speaker audio is routed to J1 pin 27. The external speaker output
goes through the DHSL Modem board and Power Supply/Interface board,
then out the
ACC 2
accessory connector on the rear panel. A separate call
alarm buzzer (DS1) alerts the operator of incoming calls and links transcall
(TC)/transadapt (TA) operation.
Wake-up
Circuitry The Front Panel Processor board uses the parity tree device U5 to monitor
input lines from the front panel (PTT, CW, clarifier and keypad) to the
processor. When one of these input lines changes state (asserted), the output of
U5 is asserted to trigger the one-shot multivibrator U4 which sends a 20 ms
pulse to the processor interrupt line (pin 2) through Q1.
Voltage Monitor,
Clock and Data
Busses Voltage detector U16 monitors and conditions the on/off power line to the
processor. At power up, U16 holds the processor in reset until the supply
voltage reaches a percentage of the set voltage (5 Vdc). If the supply voltage
drifts above or below the set voltage, U16 places the processor in reset until
the VDD is within a percentage of the set voltage.
The crystal oscillator Y1 (2.3576 MHz) provides the internal clock for the
processor at pins 42 (OSC1) and 43 (OSC2). The processor includes three
8-bit I/O data bus interfaces PA, PB and PC. The PB bus provides data to the
Display board updating the display as required. The PB bus to the DHSL
Modem board is not used. The PA bus provides specific signals to the DHSL
Modem board while the PC bus provides specific signals to the Display board.