Datexel DAT 6000 SERIES, Руководство пользователя

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DAT 6000
14
PRELIMINARY
Data Reading
The data transfer is made sending an enabling signal (ENABLE) and a clock
signal (CLK). If the ENABLE signal is high, a bit composing the reading is
provided on the output (DATA) at every clock pulse.
Every reading cycle is composed of 1 synchronism bit followed of a 16 bit word
for each analog input signal (channel). So that any reading is composed of 33
bits for 2-channels and 65 bits for 4-channels.
The synchronism bit indicates that the next bit is the most significant bit of the
first channel value (A15); the following remaining bits of this value will be
transmitted down to the least significant bit (A0). This bit will be followed by the
most significant bit of the second channel value (B15), down to the least significant
bit (B0). After the last bit, a new synchronism bit will be transmitted.
The value to be transmitted will be updated during the transmission of the
synchronism bit. During the reading cycle, the ENABLE signal must stay at
logic level HI.
The first bit after the ENABLE signal rise front will be a synchronism bit.
The synchronism bit level is high when the CLK signal is high and is low when
the CLK signal is low. Differently, each data bit is updated on the CLK rise front
and mantains its level until the next CLK rise front.
At any moment it is possible to send a rise front on the ENABLE signal to
restart the reading cycle (by the synchronism bit).
The ‘Debounce Filter’ eliminates all the signal variations shorter than the specified
time, avoiding undesired command simulations.