Chapter 4
Signal Connections
PCI-MIO E Series User Manual
4-28
©
National Instruments Corporation
Figure 4-12. Typical Pretriggered Acquisition
SCANCLK Signal
SCANCLK is an output-only signal that generates a pulse with the
leading edge occurring approximately 50 to 100 ns after an A/D
conversion begins. The polarity of this output is software-selectable but
is typically configured so that a low-to-high leading edge can clock
external analog input multiplexers indicating when the input signal has
been sampled and can be removed. This signal has a 400 to 500 ns pulse
width and is software enabled. Figure 4-13
shows the timing for the
SCANCLK signal.
Figure 4-13. SCANCLK Signal Timing
Don't Care
0
1
2
3
1
0
2
2
2
TRIG1
TRIG2
STARTSCAN
CONVERT*
Scan Counter
t w
t w = 400 to 500 ns
t d = 50 to 100 ns
td
CONVERT*
SCANCLK