Index
PCI-MIO E Series User Manual
I -12
©
National Instruments Corporation
output timing (figure), 4-32
triggers
analog, 3-13 to 3-16
above-high-level analog triggering
mode (figure), 3-14
below-low-level analog triggering
mode (figure), 3-14
block diagram, 3-13
high-hysteresis analog triggering
mode (figure), 3-15
inside-region analog triggering mode
(figure), 3-15
low-hysteresis analog triggering
mode (figure), 3-15
PFIO/TRIG1 pin (note), 3-13
RTSI triggers, 3-18 to 3-19
specifications
PCI-MIO-16E-1 and
PCI-MIO-16E-4, A-10
PCI-MIO-16XE-10, A-18
PCI-MIO-16XE-50, A-25
troubleshooting. See questions about
PCI-MIO E Series boards.
U
UISOURCE signal, 4-40
unipolar input. See input polarity and range.
unipolar output, 3-11 to 3-12
unpacking the PCI-MIO E Series, 1-7
UPDATE* signal, 4-38 to 4-40
input timing (figure), 4-39
output timing (figure), 4-39
V
VCC signal
PCI-MIO-16E-1 and PCI-MIO-16E-4,
4-6
PCI-MIO-16XE-10, 4-7
PCI-MIO-16XE-50, 4-9
VirtualBench application software, 1-3
voltage output
PCI-MIO-16E-1 and PCI-MIO-16E-4,
A-7 to A-8
PCI-MIO-16XE-10, A-16
PCI-MIO-16XE-50, A-23
W
waveform generation timing connections,
4-37 to 4-40
UISOURCE signal, 4-40
UPDATE* signal, 4-38 to 4-40
WFTRIG signal, 4-37 to 4-38
WFTRIG signal, 4-37 to 4-38
input timing (figure), 4-38
output timing (figure), 4-38
wiring considerations, 4-48