PCIe-AIO14 User Manual (Rev 1.2)
- 8 -
http://www.daqsystem.com
3.3 Ananlog Signal MUX
Multichannel data acquisition is implemented by multiplexing time-division
multiplexed (MUX) for 16 signal inputs into one ADC
AINP0
AINP30
16 to 1
MUX
Analog F/E,
ADC1
AINN0
AINN30
16 to 1
MUX
AIN_A
16 to 1
MUX
Analog F/E,
ADC2
16 to 1
MUX
AIN_B
AINP2
AINP28
AINN2
AINN28
AINP1
AINP31
AINN1
AINN31
AINP3
AINP29
AINN3
AINN29
AGND
AGND
[Fig 3-4. Analog Signal MUX]
When one channel block is composed of a plurality of data channel selections, the interchannel
acquisition interval is a maximum sampling rate of 2Msps supported by the chip, and the interval
between blocks becomes the set sampling rate.
Figure 3-5 shows that when MUX channels are changed and collected when 'CH0', 'CH1',
'CH7', 'CH8' channel setting and 'Sampling Rate' value are set to '100000' (100ksps) Timing.
-
A
IN
0
/1
A
D
-
A
IN
2
/3
A
D
-
A
IN
1
4
/1
5
A
D
-
A
IN
1
6
/1
7
A
D
-
A
IN
0
/1
A
D
-
A
IN
2
/3
A
D
-
A
IN
1
4
/1
5
A
D
-
A
IN
1
6
/1
7
A
D
-
A
IN
0
/1
A
D
-
A
IN
2
/3
A
D
-
A
IN
1
4
/1
5
A
D
-
A
IN
1
6
/1
7
A
D
-
A
IN
0
/1
A
D
- CH 0, 1, 7, 8 ( ), 100Ksps
1/2Msps = 500nsec
1/100Ksps = 10usec
[Fig 3-5. Data Collection MUX Timing]
