Dalsa Piranha 2 Series, Руководство пользователя

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20 Piranha 2 User’s Manual
03-032-00493-14 Teledyne DALSA
Table 6: Piranha 2 40MHz Timing (Fixed Integration Mode)
Symbol Definition Min (ns) Typ
(ns) Max
(ns)
tw SYN C The m inim u m low w id th of the EXSYN C
p u lse w hen not in SMART EXSYN C
m od e. 100
tw SYN C
(SMART)
*
The m inim u m low w id th of the EXSYN C
p u lse w hen in SMART EXSYN C m od es to
gu arantee the p hotosites are reset.
2,000
tw SYN C_IN T The m inim u m w id th of the high p u lse
w hen the ―SMART EXSYNC‖ feature is
tu rned off 100
tw SYN C_IN T
(SMART)
*
Is the integration time w hen the ―SMART
EXSYNC‖ feature is available and turned
on. N ote that the m inim u m tim e is
necessary to gu arantee p rop er op eration.
2,000
tLIN E PERIOD
(t
LP
)
The m inim u m and m axim u m line tim es
m ad e u p of tTransfer, tREADOUT p lu s
tOVERH EAD to m eet sp ecifications. 53,190 (8K4T)
106,382 (8K2T)
40,485 (6K4T)
80,645 (6K2T)
27,624 (4K4T)
54,054 (4K2T)
28,248 (2K2T)
15,313 (1K2T)
10
6
tTransfer The tim e from the recep tion of the falling
ed ge of EXSYN C to the rising ed ge of
LVAL w hen pretrigger is set to zero.
Pretrigger red u ces the nu m ber of clocks to
the rising edge of LVAL but doesn’t
change the tim e to the first valid p ixel. If
the fixed integration tim e m od e of
op eration is available and selected then
the integration tim e is ad d ed to the
sp ecified valu e. 1,420 +/ -50
tw Fixed Int. Fixed Integration Tim e m od e of op eration
for variable exsync frequ ency. 800 t
LP
–
2,000
tREADOUT Is the nu m ber of p ixels p er tap tim es the
read ou t clock p eriod . Pretrigger = 0. 51,200 (8K4T)
102,400 (8K2T)
38,400 (6K4T)
76,800 (6K2T)
25, 600 (4K4T)
51,200 (4K2T)
25,600 (2K2T)
12,800 (1K2T)
tOVERH EAD Is the nu m ber of p ixels that m u st elap se
after the falling ed ge of LVAL before the
EXSYN C signal can be asserted . This tim e
is u sed to clam p the internal analog
electronics 540+/ -50
thPR Ap p lies w hen the PRIN exp osu re control
featu re is enabled . The PRIN signal m u st
be held a m inim u m tim e after the
EXSYN C falling ed ge to avoid losing the
integrated charge 0
tw PR_LOW Minim u m Low tim e to assu re com p lete 2,000 +/ - 200
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