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7.Electrical Interface
© 2023 China Daheng Group, Inc. Beijing Image Vision Technology Branch 85
Parameter
Test condition
Value (μs)
Rising edge delay
VIN=5V
3.02
~
6.96
VIN=12V
2.46
~
5.14
Falling edge delay
VIN=5V
6.12
~
17.71
VIN=12V
8.93
~
19.73
Table 7-7 Delay time of opto-isolated input circuit in typical application environment
TRIGIN_F_DELAY
TRIGIN_R_DELAY
2V
0.8V
INPUT0
LINE0+
Figure 7-7 Parameter of opto-isolated input circuit
Rising time delay (TRIGIN_R_DELAY): the time required for the response to the decrease to 0.8V of
INPUT0 from 50% rising of LINE0+
Falling time delay (TRIGIN_F_DELAY): the time required for the response to the rise to 2V of INPUT0
from 50% falling of LINE0+
7.3.2.2.
Line1 (Opto-isolated Output) Circuit
Hardware schematics of opto-isolated output circuit is shown below.
1
2
8
7
6
4
5
3
OUTPUT1
Rexternal
EXVCC
Line1+
Line1-
External Circuit
Camera internal circuit
Figure 7-8 Opto-isolated output circuit (MER2/ME2P/ME2L)
Rexternal
EXVCC
Line1+
Line0/1-
OUTPUT1
1
6
2
5
3
4
External Circuit
Figure 7-9 Opto-isolated output circuit (ME2S)