Cypress S29GL01GP, Руководство пользователя

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Document Number: 002-00886 Rev. *B Page 76 of 83
S29GL01GP
S29GL512P
S29GL256P
S29GL128P
13. Advance Information on S29GL-S Eclipse 65 nm MirrorBit
Power-On and Warm Reset Timing
At power on, the flash requires additional time in the reset state to self configure than it does during a warm reset. Table and
Figure 13.1 and Figure 13.2 detail the power on and warm reset timing requirements for the GL-P, and GL-S flash.
Notes:
1. N/A = Not Applicable.
2. For GL-S, t
RP
+ t
RH
must not be less than t
RPH.
Figure 13.1
Power-Up Reset Timing
Note:
The sum of t
RP
and t
RH
must be equal to or greater than t
RPH.
Power On and Warm Reset Timing Requirements
Parameter Description Type GL-P GL-S
Power on Reset
t
VCS
V
CC
Setup Time to first access min 35 µs 300 µs
t
VIOS
V
IO
Setup Time to first access min 35 µs 300 µs
t
RPH
RESET# Low to CE# Low min 35 µs 35 µs
t
RP
RESET# Low to RESET# High min 35 µs 200 ns (2)
t
RH
RESET# High to CE# Low min 200 ns 50 ns (2)
t
CEH
CE# High to CE# Low min N/A 20 ns
Warm Reset
t
RPH
RESET# Low to CE# Low min 35 µs 35 µs
t
RP
RESET# Low to RESET# High min 35 µs 200 ns (2)
t
RH
RESET# High to CE# Low min 200 ns 50 ns (2)
t
CEH
CE# High to CE# Low min N/A 20 ns