Cypress S29GL01GP, Руководство пользователя

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Document Number: 002-00886 Rev. *B Page 6 of 83
S29GL01GP
S29GL512P
S29GL256P
S29GL128P
2. Input/Output Descriptions & Logic Symbol
Table identifies the input and output package connections provided on the device.
Input/Output Descriptions
Symbol Type Description
A25–A0 Input
Address lines for GL01GP
A24–A0 for GL512P
A23–A0 for GL256P,
A22–A0 for GL128P.
DQ14–DQ0 I/O Data input/output.
DQ15/A-1 I/O
DQ15: Data input/output in word mode.
A-1: LSB address input in byte mode.
CE# Input Chip Enable.
OE# Input Output Enable.
WE# Input Write Enable.
V
CC
Supply Device Power Supply.
V
IO
Supply Versatile IO Input.
V
SS
Supply Ground.
NC No Connect Not connected internally.
RY/BY# Output
Ready/Busy. Indicates whether an Embedded Algorithm is in progress or complete. At V
IL
, the device
is actively erasing or programming. At High Z, the device is in ready.
BYTE# Input
Selects data bus width. At VIL, the device is in byte configuration and data I/O pins DQ0-DQ7 are
active and DQ15/A-1 becomes the LSB address input. At VIH, the device is in word configuration and
data I/O pins DQ0-DQ15 are active.
RESET# Input Hardware Reset. Low = device resets and returns to reading array data.
WP#/ACC Input
Write Protect/Acceleration Input. At V
IL
, disables program and erase functions in the outermost
sectors. At V
HH
, accelerates programming; automatically places device in unlock bypass mode.
Should be at V
IH
for all other conditions. WP# has an internal pull-up; when unconnected, WP# is at
V
IH
.