MB95310L/370L Series
Document Number: 002-07519 Rev. *A
Page 53 of 80
*1: This is the default LVD reset clear threshold: 1.93 V
0.10 V. It can also be set to 2.40 V
0.15 V or 2.95 V
0.15 V.
*2: If the LVD reset clear threshold is set to 2.95 V
0.15 V, the slope from 10 MHz to 16.25 MHz should be a horizontal line.
*3: The operating voltage becomes 3.1 V if the LVD reset clear threshold is set to 2.95 V
0.15 V.
*4: The source clock frequency becomes 14.375 MHz if the LVD reset clear threshold is set to 2.40 V
0.15 V.
18.4.3
External Reset
(V
CC
= 3.0 V
10%, V
SS
= 0.0 V, T
A
=
40
C to
85
C)
*1: See “(2) Source Clock/Machine Clock” for t
MCLK
.
*2: The oscillation time of an oscillator is the time for it to reach 90% of its amplitude. The crystal oscillator has an oscillation time of
between several ms and tens of ms. The ceramic oscillator has an oscillation time of between hundreds of µs and several ms.
The external clock has an oscillation time of 0 ms. The CR oscillator clock has an oscillation time of between several µs and several
ms.
Parameter
Symbol
Value
Unit
Remarks
Min
Max
RST “L” level
pulse width
t
RSTL
2 t
MCLK
*
1
—
ns
In normal operation
Oscillation time of the oscillator*
2
100
—
µs
In stop mode, subclock mode, subsleep mode,
watch mode, and power-on
100
—
µs
In time-base timer mode
Operating voltage (V)
3.6
16 kHz
3 MHz
7.875 MHz
*4
16.25 MHz
Source clock frequency (F
SP
)
2.7
*3
2.03
*1
*2
• Operating voltage - Operating frequency (When T
A
=
5
C to
35
C)
With the on-chip debug function
