MB95310L/370L Series
Document Number: 002-07519 Rev. *A
Page 55 of 80
18.4.5
Peripheral Input Timing
(V
CC
= 3.0 V
10%, V
SS
= 0.0 V, T
A
=
40
C to
85
C)
*: See “(2) Source Clock/Machine Clock” for t
MCLK
.
18.4.6
UART/SIO, Serial I/O Timing
(V
CC
= 3.0 V
10%, AV
SS
= V
SS
= 0.0 V, T
A
=
40
C to
85
C)
*: See “(2) Source Clock/Machine Clock” for t
MCLK
.
Parameter
Symbol
Pin name
Value
Unit
Min
Max
Peripheral input “H” pulse width
t
ILIH
INT00 to INT07, EC0, EC1, ADTG
2 t
MCLK
*
—
ns
Peripheral input “L” pulse width
t
IHIL
2 t
MCLK
*
—
ns
Parameter
Symbol
Pin name
Condition
Value
Unit
Min
Max
Serial clock cycle time
t
SCYC
UCK0, UCK1
Internal clock
operation output pin:
C
L
= 80 pF
1 TTL
4 t
MCLK
*
—
ns
UCK
UO time
t
SLOVI
UCK0, UCK1,
UO0, UO1
190
190
ns
Valid UI
UCK
t
IVSHI
UCK0, UCK1,
UI0, UI1
2 t
MCLK
*
—
ns
UCK
valid UI hold time
t
SHIXI
UCK0, UCK1,
UI0, UI1
2 t
MCLK
*
—
ns
Serial clock “H” pulse width
t
SHSL
UCK0, UCK1
External clock
operation output pin:
C
L
= 80 pF
1 TTL
4 t
MCLK
*
—
ns
Serial clock “L” pulse width
t
SLSH
UCK0, UCK1
4 t
MCLK
*
—
ns
UCK
UO time
t
SLOVE
UCK0, UCK1,
UO0, UO1
—
190
ns
Valid UI
UCK
t
IVSHE
UCK0, UCK1,
UI0, UI1
2 t
MCLK
*
—
ns
UCK
valid UI hold time
t
SHIXE
UCK0, UCK1,
UI0, UI1
2 t
MCLK
*
—
ns
V
CC
1.5 V
V
SS
Hold condition in stop mode
Set the slope of rising to
a value below 20 mV/ms.
INT00 to INT07,
EC0, EC1, ADTG
0.8 V
CC
0.8 V
CC
0.2 V
CC
0.2 V
CC
t
ILIH
t
IHIL