CY8CKIT-046 PSoC® 4 L-Series Pioneer Kit Guide, Doc. #: 002-03344 Rev. *D
77
Appendix
Figure A-22. F-RAM Read Packet Structure
As the figures show, operations start with the slave address followed by the memory address. For
write operations, the bus master sends the slave address and memory address followed by one or
more data bytes. Each byte of data is written to consecutive locations in the memory, and the mem-
ory generates an acknowledgement condition.
For 'Current Address Read' and 'Sequential Read', the bus master sends only the slave address.
The memory address used is the same address that was set by the previous 'Write' or 'Selective
Read' operation. For 'Selective Read' operations, after receiving the complete slave address and
memory address, the memory will begin shifting data from the current address on the next clock
Note:
Visit the
for code examples and the Arduino library for inter-
facing I2C F-RAM devices with the PSoC 4 family.
