CY8CKIT-046 PSoC® 4 L-Series Pioneer Kit Guide, Doc. #: 002-03344 Rev. *D
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3.
Kit Operation
This chapter introduces you to the various features of the PSoC 4 L-Series Pioneer Kit. It primarily
includes the kit block overview, programming and debugging functionality, KitProg USB-UART and
USB-I2C bridges, and the method to update the KitProg firmware.
3.1
Theory of Operation
The PSoC 4 L-Series Pioneer Kit is built around the PSoC 4200L device.
shows the block
diagram of the PSoC 4200L device. Refer to the
for details on device fea-
tures.
Figure 3-1. PSoC 4200L Block Diagram
shows the block diagram for the PSoC 4 L-Series Pioneer Kit.
PSoC4200L
Architecture
32-bit
AHB-Lite
Deep Sleep
Hibernate
Active/Sleep
CPU Subsystem
SRAM
32 KB
SRAM Controller
ROM
8 KB
ROM Controller
FLASH
256 KB
Read Accelerator
SPCIF
SWD/TC
NVIC, IRQMX
Cortex
M0
48 MHz
FAST MUL
System Interconnect (Multi Layer AHB)
DataWire/
DMA (32 Ch)
Initiator
I
/
O Subsystem
80x GPIO, 14x GPIO_OVT, 2x SIO
IOSS GPIO
(13x ports)
Peripherals
System Resources
Power
Clock
WDT
ILO
Reset
Clock Control
IMO
Sleep Control
PWRSYS
REF
POR
LVD
NVLatches
BOD
WIC
Reset Control
XRES
Peripheral Interconnect
PCLK
8x TCPWM
LCD
4x SCB-
I2C/SPI/UART
2x LP Comparator
2x Capsense
Port Interface & Digital System Interconnect (DSI)
USB-FS
512B
FS-PHY
CHG-DET
Power Modes
SAR
MUX
SAR ADC
(12-bit)
x1
Programmable
Analog
CTBm
x2
2x OpAmp
2xPLL
ECO
2x CAN
Programmable
Digital
x8
...
UDB
UDB
WCO
High Speed I/O Matrix