Cypress Semiconductor CY7C1316JV18 Скачать руководство пользователя страница 23 | Manualshive

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CY7C1316JV18, CY7C1916JV18
CY7C1318JV18, CY7C1320JV18

Document Number: 001-15271 Rev. *B

Page 23 of 26

Switching Waveforms

Figure 3. Read/Write/Deselect Sequence

[24, 25, 26]

READ

READ

READ

NOP

NOP

WRITE

WRITE

NOP

1

2

3

4

5

6

7

8

9

10

Q40

t

KHCH

tCO

t

tHC

t

tHA

tSD

tHD

tKHCH

tSD

tHD

DON’T CARE

UNDEFINED

tCLZ

tDOH

tCHZ

SC

tKH

tKHKH

tKL

tCYC

A0

D20

D21

D30

D31

Q00

Q11

Q01

Q10

A1

A2

A3

A4

Q41

tCCQO

tCQOH

tCCQO

tCQOH

tKL

tCYC

K

K

LD

R/W

A

DQ

C

C#

CQ

CQ#

SA

tKH

tKHKH

t

CQD

t

CQDOH

tCQH

tCQHCQH

Notes

24. Q00 refers to output from address A0. Q01 refers to output from the next internal burst address following A0, that is, A0 + 1.
25. Outputs are disabled (High-Z) one clock cycle after a NOP.
26. In this example, if address A2 = A1, then data D20 = Q10 and D21 = Q11. Write data is forwarded immediately as read results. This note applies to the whole diagram.

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Содержание CY7C1316JV18

Страница 1: ...chronous peripheral circuitry and a one bit burst counter Addresses for read and write are latched on alternate rising edges of the input K clock Write data is registered on the rising edges of both K...

Страница 2: ...ter Read Add Decode Read Data Reg R W DQ 7 0 Output Logic Reg Reg Reg 8 8 16 8 NWS 1 0 VREF Write Add Decode 8 20 C C 8 LD Control CQ CQ R W DOFF 1M x 8 Array 1M x 8 Array 8 Write Reg Write Reg CLK A...

Страница 3: ...Q 17 0 Output Logic Reg Reg Reg 18 18 36 18 BWS 1 0 VREF Write Add Decode 18 20 C C 18 LD Control Burst Logic A0 A 19 1 CQ CQ R W DOFF 512K x 18 Array 512K x 18 Array 19 18 Write Reg Write Reg CLK A 1...

Страница 4: ...S VDDQ NC NC DQ0 M NC NC NC VSS VSS VSS VSS VSS NC NC NC N NC NC NC VSS A A A VSS NC NC NC P NC NC DQ7 A A C A A NC NC NC R TDO TCK A A A C A A A TMS TDI CY7C1916JV18 2M x 9 1 2 3 4 5 6 7 8 9 10 11 A...

Страница 5: ...C A A NC NC DQ0 R TDO TCK A A A C A A A TMS TDI CY7C1320JV18 512K x 36 1 2 3 4 5 6 7 8 9 10 11 A CQ NC 144M NC 36M R W BWS2 K BWS1 LD A NC 72M CQ B NC DQ27 DQ18 A BWS3 K BWS0 A NC NC DQ8 C NC NC DQ28...

Страница 6: ...inputs are multiplexed for both read and write operations Internally the device is organized as 2M x 8 2 arrays each of 1M x 8 for CY7C1316JV18 and 2M x 9 2 arrays each of 1M x 9 for CY7C1916JV18 1M...

Страница 7: ...Input DLL Turn Off Active LOW Connecting this pin to ground turns off the DLL inside the device The timing in the DLL turned off operation is different from that listed in this data sheet For normal o...

Страница 8: ...ock rise the data presented to D 17 0 is latched and stored into the 18 bit write data register provided BWS 1 0 are both asserted active On the subsequent rising edge of the negative input clock K th...

Страница 9: ...chips use a Delay Lock Loop DLL that is designed to function between 120 MHz and the specified maximum clock frequency During power up when the DOFF is tied HIGH the DLL is locked after 1024 cycles of...

Страница 10: ...D 8 0 is written into the device D 17 9 remains unaltered H L L H During the data portion of a write sequence CY7C1316JV18 only the upper nibble D 7 4 is written into the device D 3 0 remains unaltere...

Страница 11: ...into the device D 35 9 remains unaltered L H H H L H During the Data portion of a write sequence only the lower byte D 8 0 is written into the device D 35 9 remains unaltered H L H H L H During the Da...

Страница 12: ...lling edge of TCK Instruction Register Three bit instructions can be serially loaded into the instruction register This register is loaded when it is placed between the TDI and TDO pins as shown in TA...

Страница 13: ...n register Once the data is captured it is possible to shift out the data by putting the TAP into the Shift DR state This places the boundary scan register between the TDI and TDO pins PRELOAD places...

Страница 14: ...oller follows 9 TEST LOGIC RESET TEST LOGIC IDLE SELECT DR SCAN CAPTURE DR SHIFT DR EXIT1 DR PAUSE DR EXIT2 DR UPDATE DR 1 0 1 1 0 1 0 1 0 0 0 1 1 1 0 1 0 1 0 0 0 1 0 1 1 0 1 0 0 1 1 0 SELECT IR SCAN...

Страница 15: ...H Voltage 0 65VDD VDD 0 3 V VIL Input LOW Voltage 0 3 0 35VDD V IX Input and Output Load Current GND VI VDD 5 5 A 0 0 1 2 29 30 31 Boundary Scan Register Identification Register 0 1 2 106 0 1 2 Instru...

Страница 16: ...H TDI Hold after Clock Rise 5 ns tCH Capture Hold after Clock Rise 5 ns Output Times tTDOV TCK Clock LOW to TDO Valid 10 ns tTDOX TCK Clock LOW to TDO Invalid 0 ns TAP Timing and Test Conditions Figur...

Страница 17: ...uction Codes Instruction Code Description EXTEST 000 Captures the input and output ring contents IDCODE 001 Loads the ID register with the vendor ID code and places the register between TDI and TDO Th...

Страница 18: ...0 3L 7 8P 35 10E 63 1H 91 1M 8 9R 36 10D 64 1A 92 1L 9 11P 37 9E 65 2B 93 3N 10 10P 38 10C 66 3B 94 3M 11 10N 39 11D 67 1C 95 1N 12 9P 40 9C 68 1B 96 2M 13 10M 41 9D 69 3D 97 3P 14 11N 42 11B 70 3C 98...

Страница 19: ...are stable take DOFF HIGH The additional 1024 cycles of clocks are required for the DLL to lock DLL Constraints DLL uses K clock as its synchronizing input The input must have low phase jitter which i...

Страница 20: ...ote 17 VDDQ 2 0 12 VDDQ 2 0 12 V VOH LOW Output HIGH Voltage IOH 0 1 mA Nominal Impedance VDDQ 0 2 VDDQ V VOL LOW Output LOW Voltage IOL 0 1 mA Nominal Impedance VSS 0 2 V VIH Input HIGH Voltage VREF...

Страница 21: ...Junction to Ambient Test conditions follow standard test methods and procedures for measuring thermal impedance in accordance with EIA JESD51 28 51 C W JC Thermal Resistance Junction to Case 5 91 C W...

Страница 22: ...45 ns tDOH tCHQX Data Output Hold after Output C C Clock Rise Active to Active 0 45 ns tCCQO tCHCQV C C Clock Rise to Echo Clock Valid 0 45 ns tCQOH tCHCQX Echo Clock Hold after C C Clock Rise 0 45 ns...

Страница 23: ...tKL tCYC A0 D20 D21 D30 D31 Q00 Q11 Q01 Q10 A1 A2 A3 A4 Q41 tCCQO tCQOH tCCQO tCQOH tKL tCYC K K LD R W A DQ C C CQ CQ SA tKH tKHKH tCQD tCQDOH tCQH tCQHCQH Notes 24 Q00 refers to output from address...

Страница 24: ...Fine Pitch Ball Grid Array 13 x 15 x 1 4 mm Commercial CY7C1916JV18 300BZC CY7C1318JV18 300BZC CY7C1320JV18 300BZC CY7C1316JV18 300BZXC 51 85180 165 Ball Fine Pitch Ball Grid Array 13 x 15 x 1 4 mm P...

Страница 25: ...0 05 M C B A 0 15 4X 0 35 0 06 SEATING PLANE 0 53 0 05 0 25 C 0 15 C PIN 1 CORNER TOP VIEW BOTTOM VIEW 2 3 4 5 6 7 8 9 10 10 00 14 00 B C D E F G H J K L M N 11 11 10 9 8 6 7 5 4 3 2 1 P R P R K M N L...

Страница 26: ...urce Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as speci...

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