Curtiss-Wright
Parvus DuraNET 20-11
Chapter 5 Specifications
MNL-0656-01 Rev A8
ECO-N/A
Effective: 16 Nov 21
Page 33 of 44
C
HAPTER
5
S
PECIFICATIONS
T
ECHNICAL
S
PECIFICATIONS
A
RCHITECTURE
Packet processor: Vitesse Carrier Grade Ethernet Switch Engine
Switching: Non-Blocking OSI Data Layer 2, IPv4 / IPv6 Multicast, Low-Latency, Auto-MDI/MDIX,
Auto- Negotiation, Auto-Detect; Speed Auto-Sensing, Auto-Crossover, Full/Half Duplex Modes,
QoS
Management processor: Embedded MIPS CPU with DDR-2 Memory
Networking software: Vitesse CE Services Carrier Ethernet Application
P
ORTS
8x 10/100/1000BaseT Gigabit Ethernet ports
RS-232 management console
Power input & data zeroize
L
AYER
2
S
WITCHING
Port control: port-speed, duplex mode, flow control, port frame size (jumbo frames), port state,
port status (link monitoring), port statistics (MIB counters)
Quality of Service (QoS) traffic prioritization and queuing: 8 priorities,8 CoS queues per port,
dtrict or deficit-weighted RR scheduling, shaping/policing per queue and per port, Storm Control
VLAN: 8K MAC addresses, 4K VLANs, 802.1Q Static VLAN, Protocol-Based VLAN, MRP,
MVRP, MVR, IEEE-80210ad Provider Bridge, Link Aggregation (IEEE-802.3ad)
IEEE-802.1 D/w/s (Spanning Tree, Rapid Spanning Tree, Multiple Spanning Tree Protocol)
L2 IEEE-1588v2 Precision Timing Protocol (PTP)
L
AYER
3
R
OUTING
Layer 3 IPv4 / IPv6 Unicast static routing support for IP routing to attached WAN/radio ports