Cronyx E1 - L/S, Руководство по установке и эксплуатации

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© 2006 Cronyx
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Section 4. Control From the Console
«Port» Menu for V.35 / RS-530 / RS-232 / X.21 Digital Port
The «Port» menu sets the modes of the digital port. For the V.35 / RS-530 / RS-232 / X.21
port the following parameters should be set:
Port
1. Timeslots...
4. Mode: Sync
5. Receive clock: Receive
6. Transmit data strobe: Normal (data valid on falling edge)
7. Receive data strobe: Normal (data valid on falling edge)
8. HDLC buffer: Disabled
9. CTS = 1
Command: _
The
«Timeslots»
command assigns timeslots of the data port (in «Framing: E1» mode
only).
The «CTS» command selects on of the four rules of generating of the CTS output line
state: «1», «RTS», «CD» or «RTS*CD».
Synchronous Mode
In the synchronous ( «Mode: Sync») mode the following parameters should be set:
• «Receive clock» - input clock source of the digital port.
• «Transmit data strobe» – TXC line inversion;
• «Receive data strobe» – RXC line inversion;
• «HDLC buffer» – enable or disable the HDLC buffer.
The «Receive clock» command sets the input clock source of the digital port: from the
E1 link («Receive»), from external clock signal (ETC) of the digital port or from ERC
external clock signal («External»). External clock source is used when connecting to
DCE devices which do not support an external synchronization from a digital port (RS-
232, V.35, RS-530). In this case the device transmits data using clock signal from ERC
input line. The phase equalization of data at the RXD output line of the digital port for
ERC clocks is executed using FIFO buffer. To ensure the correct buffer operation (with
no overruns/underruns) the frequency of clocks received from the line should equal to
the frequency at ERC input. This condition is met when the data link has a single clock
source. Otherwise, recurrent errors will occur due to overruns or underruns of FIFO
buffer. The rate of such errors depends on the difference between the two frequencies.
When «Internal» or «From Link» synchronization mode is used, data signal TXD is
delayed in relation to TXC clock. Summary delay is formed by cable delay and digital
interfaces delay of modem and connected device. As a result of this delay errors can oc-