Cronyx E1 - L/S, Руководство по установке и эксплуатации

Страница: 22 / 52

Modem-Converter E1-L/S
© 2006 Cronyx
DTE emulation, external transmit and receive clocks
The «Receive clock: External» mode is used when connecting to DCE devices which do
not support an external synchronization from a digital port (RS-232, V.35, RS-530). In
this case E1-L device receives data at the digital port using clock signal from ETC input
line and transmits data using clock signal from ERC input line. The phase equaliza-
tion of data at the RXD output line of the digital port for ERC clocks is executed using
FIFO buffer. To ensure the correct buffer operation (with no overruns/underruns) the
frequency of clocks received from the line should equal to the frequency at ERC input.
This condition is met when the data link has a single clock source. Otherwise, recurrent
errors will occur due to overruns or underruns of FIFO buffer. The rate of such errors
depends on the difference between the two frequencies.
DɋE
RXC
TXC
RXD
DTE
«Transmit clock: From Port»,
«Receive clock: External»
E1 link
RXD
TXD
ETC
ERC
TXD
TXD
RXD
RXC
FIFO
If the data transmitted in the link is in HDLC format you can compensate the frequen-
cies offset enabling HDLC buffer mode.
HDLC Buffer Mode
HDLS buffer mode is used when connecting digital port to the arbitrary DCE device
(e.g., device which uses independent clock source or uses separate transmit and receive
clock sources). In this case two external clock sources are used for ETC and ERC input
lines of the digital port. The TXC and RXC output lines are disabled.
The receive and transmit data paths contain intermediate data buffers for converting
the clock frequency by inserting or deleting HDLC flags. The data stream must contain
HDLC packets with the number of delimiting flags not less than 2. Maximum available
difference of frequencies is about 200 ppm.