PT-S959SDLX / PT-S959SDLXC Series User’s Manual
65
Table 6.1. POST Codes < 2 / 3 >
POST (hex)
Description
62h
South Bridge runtime services installation
63h
CPU DXE installation start
64h - 67h
CPU DXE installation start (Specific CPU module)
68h
PCI host bridge installation
69h
North Bridge DXE initialization starts
6Ah
North Bridge DXE SMM initialization starts
6Bh - 6Fh
North Bridge DXE initialization (Specific North Bridge module)
70h
South Bridge DXE initialization starts
71h
South Bridge DXE SMM initialization starts
72h
South Bridge device initialization
73h - 77h
South Bridge DXE initialization (Specific South Bridge module)
78h
ACPI module initialization
79h
CSM initialization
7Ah - 7Fh
For future AMI DXE codes reserved
80h - 8Fh
OEM DXE initialization code
90h
Boot Device Selection(BDS) Phase
91h
Driver connection start
92h
PCI bus initialization starts
93h
PCI bus hot plug controller initialization
94h
Enumerate PCI bus number
95h
PCI bus resource requests
96h
PCI bus resource allocation
97h
Console output device connection
98h
Console input device connection
99h
Super IO initialization
9Ah
USB installation start
9Bh
USB reset
9Ch
USB detection
9Dh
USB enabling
9Eh - 9Fh
For future AMI codes reserved
A0h
IDE initialization starts
A1h
IDE reset
A2h
IDE detection
A3h
IDE enabling
A4h
SCSI initialization starts
A5h
SCSI reset
A6h
SCSI detection
A7h
SCSI enabling
A8h
Confirm Password Setup
A9h
Starting of a setup
AAh
ASL for reserved (Refer to ACPI/ASL Checkpoints)
ABh
Setup input wait
ACh
ASL for reserved (Refer to ACPI/ASL Checkpoints)
ADh
Boot preparation events
AEh
Legacy boot event
AFh
Boot Service event ends
B0h
Virtual address maps run-time settings begin.
B1h
Virtual address maps of runtime configuration exit
B2h
Legacy option ROM initialization