5. Each Component Function
64
User’s Manual
Control of Transmitted Data in Half-Duplex Mode
In half-duplex mode, the transmission buffer needs to be controlled in order to prevent collision of
transmitted data. The BOX-PC uses RTS and controls the buffer with modem control register's bit 1.
Transmission and reception gate control by the register setting of port address 4006h and 4007h is
allowed only for the RS-422/485 (Serial port D). For more information see section, "General-purpose
I/O and Remote Reset" in Chapter 5.
Modem control register
(Set I/O a4H) bit 1
: 0 … RTS is High. (Disable transmission)
1 … RTS is Low. (Enable transmission)
I/O Addresses and Instructions
The I/O addresses and instructions of COM1 are shown next.
Table 5.11. I/O Addresses
I/O address DLAB Read/Write
Register
0
W
Transmitter holding register
THR
R
Receive
buffer
register
RBR
03F8H
1 W
Divisor
latch
register
DLL
1 W
Divisor
latch
register
DLM
03F9H
0
W
Interrupt enable register
IER
03FAH X
R Interrupt
ID
register
IIR
03FBH
X
W
Line control register
LCR
03FCH
X
W
Modem control register
MCR
03FDH
X
R
Line status register
LSR
03FEH
X
R
Modem status register
MSR
03FFH X R/W
Scratch
register
SCR
DLAB (Divisor Latch Access Bit) : The value in bit 7 of the line control register