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2014
congatec
AG
TS87m13
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The conga-TS87 PWR_OK input circuitry is implemented as shown below:
The voltage divider ensures that the input complies with 3.3V CMOS characteristic and also allows for carrier board designs that are not driving
PWR_OK. Although the PWR_OK input is not mandatory for the onboard power-up sequencing, it is strongly recommended that the carrier
board hardware drives the signal low until it is safe to let the module boot-up.
When considering the above shown voltage divider circuitry and the transistor stage, the voltage measured at the PWR_OK input pin may be
only around 0.8V when the 12V is applied to the module. Actively driving PWR_OK high is compliant to the COM Express specification but this
can cause back driving. Therefore, congatec recommends driving the PWR_OK low to keep the module in reset and tri-state PWR_OK when
the carrier board hardware is ready to boot.
The three typical usage scenarios for a carrier board design are:
•
Connect PWR_OK to the “power good” signal of an ATX type power supply.
•
Connect PWR_OK to the last voltage regulator in the chain on the carrier board.
•
Simply pull PWR_OK with a 1k resistor to the carrier board 3.3V power rail.
With this solution, it must be ensured that by the time the 3.3V is up, all carrier board hardware is fully powered and all clocks are stable.
To Module Power Logic
PWR_OK
R5
R1%47k5S02
TB
TBC847
R4
R1%100kS02
+V12.0_S0
R13
R1%1k00S02
R1
R1%47k5S02
R2
R1%20k0S02
