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SA70m01

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Table 14.1

Optional eDP Signal Description

Signals

Pins

Description

I/O

PU/PD Comments

eDP0_TX0-

S125

S126

eDP0 primary differential data pair 0

O LVDS

Not supported by default. AC

coupling required off-module

eDP0_TX1-

S128

S129

eDP0 primary differential data pair 1

O LVDS

eDP0_TX2-

S131

S132

eDP0 primary differential data pair 2

O LVDS

eDP0_TX3-

S137

S138

eDP0 primary differential data pair 3

O LVDS

eDP0_AUX-

S134

S135

eDP0 primary auxiliary differential pair for link management and device control

O LVDS

LCD0_VDD_EN

S133

Primary panel power enable. High enables panel VDD

O 1.8V

LCD0_BKLT_EN

S127

Primary backlight enable. High enables panel backlight

O 1.8V

LCD0_BKLT_PWM S141

Primary backlight brightness control via pulse width modulation (PWM)

O 1.8V

eDP0_HPD

S144

eDP0 Hot Plug Detect pins for primary eDP display

I 1.8V

PD 100k

100k PD present only on variants

with eDP support

eDP1_TX0-

S111

S112

eDP1 secondary differential data pair 0

O LVDS

Not supported

eDP1_TX1-

S114

S115

eDP1 secondary differential data pair 1

O LVDS

eDP1_TX2-

S117

S118

eDP1 secondary differential data pair 2

O LVDS

eDP1_TX3-

S120

S121

eDP1 secondary differential data pair 3

O LVDS

eDP1_AUX-

S108

S109

eDP1 secondary auxiliary differential pair for link management and device

control

O LVDS

LCD1_VDD_EN

S116

Secondary panel power enable. High enables panel VDD

O 1.8V

Not connected

LCD1_BKLT_EN

S107

Secondary panel backlight enable. High enables panel backlight

O 1.8V

LCD1_BKLT_PWM S122

Secondary panel backlight brightness control via pulse width modulation (PWM) O 1.8V

eDP1_HPD

S113

eDP1 Hot Plug Detect pins

I 1.8V

I2C_LCD_DAT

S140

I2C data to read LCD display EDID EEPROMs. Possible EDID EEPROM address

conflicts may occur if multiple displays are implemented

I/O OD

1.8V

PU 1k3

Optional - eDP panel information is

usually via the eDP auxiliary pair

I2C_LCD_CK

S139

I2C clock to read LCD display EDID EEPROMs

O 1.8V

PU 1k3

Optional - eDP panel information is

usually via the eDP auxiliary pair

Содержание 050100

Страница 1: ...SMARC conga SA7 SMARC 2 1 module based on Intel Atom Pentium and Celeron Elkhart Lake SoC User s Guide Revision 0 1 Preliminary...

Страница 3: ...information contained herein and hereby expressly disclaims any implied warranties of merchantability or fitness for any particular purpose with regard to any of the foregoing congatec GmbH assumes no...

Страница 4: ...n its original packaging Be aware that failure to comply with these guidelines will void the congatec GmbH Limited Warranty Symbols The following symbols are used in this user s guide Warning Warnings...

Страница 5: ...pon specifications will be repaired or exchanged at congatec s option and expense Customer will obtain a Return Material Authorization RMA number from congatec GmbH prior to returning the non conformi...

Страница 6: ...been made available to assist you If you still require assistance after visiting our website then contact our technical support department by email at support congatec com Terminology Term Descriptio...

Страница 7: ...DP 27 5 3 SATA 27 5 4 Gigabit Ethernet 27 5 5 USB 28 5 6 Audio HDA 28 5 7 SD Card 29 5 8 UART 29 5 9 GPIO 29 5 10 SPI 30 5 11 I2C 30 5 12 Power Control 30 6 Additional Features 33 6 1 Optional Onboar...

Страница 8: ...9 1 I O Address Assignment 63 9 2 PCI Configuration Space Map 63 9 3 I C Bus and SMBus 63 9 4 congatec System Sensors 63 10 BIOS Setup Description 64 10 1 Navigating the BIOS Setup Menu 64 10 2 BIOS...

Страница 9: ...HDMI Signal Descriptions 50 Table 16 DisplayPort 51 Table 17 MIPI CSI 2 3 51 Table 18 SDIO Signal Descriptions 52 Table 19 SPI0 Signal Descriptions 53 Table 20 eSPI SPI1 Signal Descriptions 53 Table...

Страница 10: ...variety of product development options from compact space saving designs to fully functional systems This solution allows scalability product diversification and faster time to market 1 2 conga SA7 O...

Страница 11: ...T s quad channel 8 GB 3200 MT s quad channel 4 GB 3200 MT s quad channel 16 GB 3200 MT s quad channel 8 GB 3733 MT s quad channel 8 GB 3200 MT s quad channel eMMC 64 GB 32 GB 32 GB 64 GB 32 GB 32 GB W...

Страница 12: ...DI s and one LVDS eDP DSI 1x LVDS dual channel 1x DP 1x HDMI 2 0b native Optional Interface assembly option 1x eDP 1 3 1 or 1x MIPI DSI x4 lane 1 1x DP DDI1 2 Peripheral Interfaces 1x SATA 6 Gb s Up t...

Страница 13: ...64 bit RTS Hypervisor Note We do not offer installation support for systems with less than 20 GB storage space 2 3 Mechanical Dimensions The conga SA7 has the following dimensions length of 82 mm widt...

Страница 14: ...ltage 5 4 75 5 00 5 25 Vdc Ripple 50 mVPP 0 20MHz Current 2 4 3 Rise Time The input voltages shall rise from 10 percent of nominal to 90 percent of nominal at a minimum slope of 250 V s The smooth tur...

Страница 15: ...S0 Maximum value Highest frequency mode HFM Turbo Boost The CPU was stressed to its maximum frequency S0 Peak value Highest power spike during the measurement of S0 Maximum value This state shows the...

Страница 16: ...ows 10 Intel Pentium J6426 4 2 0 3 0 GHz TBD TBD TBD TBD TBD TBD 050121 8 GB B x TBD Windows 10 Intel Celeron J6413 4 1 8 3 0 GHz TBD TBD TBD TBD TBD TBD 050122 8 GB B x TBD Windows 10 Intel Pentium N...

Страница 17: ...ial variants Operation 40 to 85 C Storage 40 to 85 C Humidity Operation 10 to 90 Storage 5 to 95 Caution The above operating temperatures must be strictly adhered to at all times When using a congatec...

Страница 18: ...1 TPM GbE PHY DP83867XS GbE PHY DP83867XS eDP to LVDS Bridge DP to TMDS Level Shifter Wi Fi BT 1x eDP or 1x MIPI DSI x4 1x DP GbE0 GbE1 Optional Not available by default congatec Board Controller 5th...

Страница 19: ...formation about this subject contact your local congatec sales representative and request the gap pad material manufacturer s specification Caution 1 The congatec heatspreaders cooling solutions are t...

Страница 20: ...ht 2021 congatec GmbH SA70m01 20 65 4 1 CSP Dimensions Lidded Variants Industrial 82 53 53 6 20 1 A A 4 23 98 34 4 17 6 63 76 74 82 2 7 x 6 mm non threaded standoff for borehole version 2 2 3 2 0 15 3...

Страница 21: ...CSP Dimensions Bare die Variants Commercial 82 53 53 1 15 0 15 Without phase changer 6 20 1 A A 2 7 2x 2 8 2X 15 16 9 3 1 1 5 A A 2 8 0 10 4 2 4X 1 4 0 10 3 0 8 4 23 98 34 4 17 6 63 76 74 82 2 7 x 6...

Страница 22: ...22 65 4 3 HSP Dimensions Lidded Variants Industrial 2 2 3 2 0 15 6 0 2 3 2 0 15 4 34 28 18 4 17 6 63 76 74 2 7 x 6 mm non threaded standoff for borehole version A A 2 8 0 10 M3x0 5p 4X 90 0 4 8X Cham...

Страница 23: ...5 4 4 HSP Dimensions Bare die Variants Commercial 1 15 0 15 Without phase changer 6 0 2 3 2 1 15 0 15 Without phase changer A A C A A 90 6 2 7 0 8 C 4 23 98 34 28 18 4 17 6 63 76 74 2 7 x 6 mm non thr...

Страница 24: ...Possible only with a custom BIOS firmware 3 The conga SA7 provides PCIe_A_REFCK PCIe_B_REFCK and PCIe_C_REFCK reference clocks to the carrier board 5 1 1 Possible Reference Clock Configuration The co...

Страница 25: ...1920x1200 60Hz dual mode DP 4096x2160 60Hz HDMI 4096x2160 60Hz Option 1 eDP or DSI eDP 3840x2160 60 Hz DSI 3200x2000 60 Hz 1 x4 lane or 4096x2304 60 Hz 2 x4 lane DP 4096x2160 60Hz HDMI 4096x2160 60Hz...

Страница 26: ...ode Note 1 LVDS channel A first channel supports an optional eDP or MIPI DSI x4 interface assembly option 2 Variants with optional eDP or MIPI DSI interface do not support LVDS interface 3 Only one MI...

Страница 27: ...not support native HDMI voltage levels 5 3 SATA The conga SA7 offers a SATA interface The interface supports SATA specification 3 2 independent DMA operation data transfer rates up to 6 0 Gb s AHCI m...

Страница 28: ...USB port mapping are shown in table 10 Table 10 Possible USB Port Mapping USB 2 0 USB 3 1 Gen 2 2 0 Host Only Dual Role Host Only Dual Role Default 4 ports TBD 2 port Option 1 4 ports 2 port TBD Opti...

Страница 29: ...provides four UART ports UART1 and UART2 via the SoC 1 UART0 and UART3 via the congatec board controller 2 Note 1 No support for legacy mode operation 2 Driver is available on the congatec website at...

Страница 30: ...iver and API The controller provides a fast mode multi master I2C bus that has maximum I2C bandwidth 5 12 Power Control The conga SA7 operates only with 5 V input voltage Its power up sequence is desc...

Страница 31: ..._STBY The CARRIER_STBY signal pin S153 is an active low output that can be used to indicate that the conga SA7 is going into suspend state where only power management functions and system memory are p...

Страница 32: ...voltage exceeds a certain voltage threshold A voltage dip after passing this threshold may lead to these circuits becoming confused thereby resulting in a malfunction To ensure this problem does not o...

Страница 33: ...s from the x86 core architecture the microcontroller increases the performance and reliability of the BIOS features even during low power mode In addition it ensures the congatec embedded feature set...

Страница 34: ...rol of the power up of the module and therefore can be used to specify the behavior of the system after an AC power loss condition Supported modes are Always On Remain Off and Last State 6 3 5 Watchdo...

Страница 35: ...ot Logo This feature allows system designers to replace the standard text output displayed during POST with their own BIOS boot logo Customized BIOS development by congatec for OEM Boot Logo is no lon...

Страница 36: ...inear Technology and a battery only solution no charger All three battery solutions are supported on the I2C bus and the SMBus This gives the system designer more flexibility when choosing the appropr...

Страница 37: ...ting Uses 10 nm process technology Note Intel Hyper Threading technology is not supported four cores execute four threads 7 1 1 1 Intel Virtualization Technology Intel Virtualization Technology Intel...

Страница 38: ...sumption of the processor by throttling the processor clock One of the advantages of this cooling policy is that passive cooling devices in this case the processor do not produce any noise Use the pas...

Страница 39: ...rom S3 PCI Express WAKE Wakes unconditionally from S3 WAKE Wakes unconditionally from S3 USB Mouse Keyboard Event When standby mode is set to S3 the standby power source must power the USB hardware in...

Страница 40: ...7 3 USB Port Mapping USB 2 0 Port 2 USB 3 0 USB 2 0 Port 1 Port 0 Port 4 Port 5 SMARC Connector Port 3 Port 2 xHCI USB 2 0 Port 1 USB 2 0 Port 0 dual role Elkhart Lake SoC OR OR USB 2 0 Port 3 USB 3 1...

Страница 41: ...logy Descriptions Term Description I Input to the module O Output from the module O OD Open drain output from the module I OD Open drain input to the module with pull up on module OD Open drain I O Bi...

Страница 42: ...P11 CSI1_RX1 2 S12 CSI0_RX0 2 P12 GND S13 GND P13 CSI1_RX2 2 S14 CSI0_RX1 2 P14 CSI1_RX2 2 S15 CSI0_RX1 2 P15 GND S16 GND P16 CSI1_RX3 2 S17 GBE1_MDI0 P17 CSI1_RX3 2 S18 GBE1_MDI0 P18 GND S19 GBE1_LI...

Страница 43: ...SPI0_CK S45 MDIO_CLK 2 P45 SPI0_DIN S46 MDIO_DAT 2 P46 SPI0_DO S47 GND P47 GND S48 I2C_GP_CK P48 SATA_TX S49 I2C_GP_DAT P49 SATA_TX S50 HDA_SYNC P50 GND S51 HDA_SDO P51 SATA_RX S52 HDA_SDI P52 SATA_RX...

Страница 44: ...PCIE_C_RST P77 PCIE_B_CKREQ S78 PCIE_C_RX SERDES_1_RX P78 PCIE_A_CKREQ S79 PCIE_C_RX SERDES_1_RX P79 GND S80 GND P80 PCIE_C_REFCK S81 PCIE_C_TX SERDES_1_TX P81 PCIE_C_REFCK S82 PCIE_C_TX SERDES_1_TX P...

Страница 45: ...O1 CAM1_PWR S110 GND P110 GPIO2 CAM0_RST S111 LVDS1_0 eDP1_TX0 DSI1_D0 P111 GPIO3 CAM1_RST S112 LVDS1_0 eDP1_TX0 DSI1_D0 P112 GPIO4 HDA_RST S113 eDP1_HPD DSI1_TE 2 P113 GPIO5 PWM_OUT S114 LVDS1_1 eDP1...

Страница 46: ...S138 LVDS0_3 eDP0_TX3 DSI0_D3 P138 SER2_RTS S139 I2C_LCD_CK P139 SER2_CTS S140 I2C_LCD_DAT P140 SER3_TX S141 LCD0_BKLT_PWM P141 SER3_RX S142 GPIO12 P142 GND S143 GND P143 CAN0_TX S144 eDP0_HPD DSI0_TE...

Страница 47: ...PWM O 1 8V LVDS1_0 LVDS1_0 S111 S112 LVDS secondary data channel differential pair 0 O LVDS LCD LVDS1_1 LVDS1_1 S114 S115 LVDS secondary data channel differential pair 1 O LVDS LCD LVDS1_2 LVDS1_2 S1...

Страница 48: ...s with eDP support eDP1_TX0 eDP1_TX0 S111 S112 eDP1 secondary differential data pair 0 O LVDS DP Not supported eDP1_TX1 eDP1_TX1 S114 S115 eDP1 secondary differential data pair 1 O LVDS DP eDP1_TX2 eD...

Страница 49: ...WM O 1 8V DSI1_D0 DSI1_D0 S111 S112 DSI1 secondary differential data pair 0 O LVDS D PHY DSI1_D1 DSI1_D1 S114 S115 DSI1 secondary differential data pair 1 O LVDS D PHY DSI1_D2 DSI1_D2 S117 S118 DSI1 s...

Страница 50: ...on drive DP1_AUX_SEL pin P107 to 1 8 V on the carrier board Table 15 1 DP Operation Over HDMI Pins Signal Descriptions Signal Pin Description I O PU PD Comment DP1_LANE0 DP1_LANE0 P92 P93 DisplayPort...

Страница 51: ...5 Pulled to GND on carrier for DP operation in dual mode DP implementations I 1 8V PD 1M Table 17 MIPI CSI 2 3 Signal Pin Description I O PU PD Comment CSI0_RX0 CSI0_RX0 S11 S12 CSI0 differential data...

Страница 52: ...1_CK CSI1_TX S1 I2C clock serial camera support link for serial cameras I O OD 1 8V I2C_CAM1_DAT CSI1_TX S2 I2C data serial camera support link for serial cameras I O OD 1 8V Table 18 SDIO Signal Desc...

Страница 53: ...input and output operations O 1 8V ESPI_CS0 P54 ESPI master chip selet outputs Driving Chip Select low selects a particular eSPI slave for the transaction Each of the eSPI slaves is connected to a de...

Страница 54: ...not support I2S Table 22 HDA I2S Signal Descriptions Signal Pin Description I O PU PD Comment HDA_SYNC S50 HD audio serial bus synchronization I O 1 8V HDA_SDO S51 HD audio serial data output to code...

Страница 55: ...R2 O 1 8V SER2_CTS P139 Clear to Send handshake line for SER2 I 1 8V PU 100k 1 8V SER3_TX P140 Asynchronous serial data output port 3 O 1 8V congatec Board Controller UART SER3_RX P141 Asynchronous se...

Страница 56: ...rs are on module O USB SS Note The conga SA7 does not support USB OTG Table 26 PCIe Signal Description Signal Name Pin Description I O PU PD Comment PCIE_A_TX PCIE_A_TX P89 P90 Differential PCIe link...

Страница 57: ...Data Pair O PCIE Not supported SERDES_1_RX SERDES_1_RX S78 S79 Differential SERDES 1 Receive Data Pair I PCIE SERDES_0_TX SERDES_0_TX S29 S30 Differential SERDES 0 Transmit Data Pair O PCIE SERDES_0_...

Страница 58: ...3 S26 S27 Bidirectional transmit receive pair 3 to magnetics Media Dependent Interface I O GBE MDI GBE0_LINK100 GBE1_LINK100 P21 S19 Link speed indication LED for 100 Mb s O OD 3 3V Up to 24 mA LED cu...

Страница 59: ...8V Controlled by the cBC Default BIOS setting Pulse Width Modulation output GPIO6 TACHIN P114 Bidirectional general purpose input output Alternate use Tachometer input TACHIN I O 1 8V Controlled by th...

Страница 60: ...10k SLEEP S149 Sleep indicator from carrier board May be sourced from user Sleep button or carrier logic Carrier to float the line in in active state Active low level sensitive Should be de bounced on...

Страница 61: ...then a low on the module FORCE_RECOV pin may invoke the SOC native Force Recovery mode such as over a Serial Port For x86 systems this signal may be used to load BIOS defaults Pulled up on module Driv...

Страница 62: ...ull down resistors should change the configuration of the signals listed in the above table 3 External resistors may override the internal strap states and cause the SMARC module to malfunction and or...

Страница 63: ...The conga SA7 offers the following sensors and monitors temperature sensors CPU temperature based on CPU Digital Thermal Sensor Board temperature sensor located on the Board Controller voltage sensors...

Страница 64: ...etup screen The initial production BIOS for conga SA7 is identified as SA70R1xx where R is the identifier for a BIOS ROM file 1 is the so called feature number and xx is the major and minor revision n...

Страница 65: ...BIOS from external flash refer to the AN7_External_BIOS_Update pdf application note on the congatec website at http www congatec com 10 4 Supported Flash Devices The conga SA7 supports the following...

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