RC56D, RC336D, and RC144D Modem Device Sets Designer’s Guide
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Conexant
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modem DGND pins to the digital ground plane area and AGND pins to the analog ground plane area. Typically, separate
the collective digital ground plane area from the collective analog ground plane area by a fairly straight gap. There should
be no inroads of digital ground plane area extending into the analog ground plane area or visa versa.
2. In a 4-layer design, provide separate digital and analog ground planes covering the corresponding digital and analog
circuits (exclusive of the DAA), respectively. Connect all modem DGND pins to the digital ground plane and AGND pins
to the analog ground plane. Typically, separate the digital ground plane from the analog ground plane by a fairly straight
gap.
3. In a design which needs EMI filtering, define an additional “chassis” section adjacent to the bracket end of a plug-in card.
Most EMI components (usually ferrite beads/capacitor combinations) can be positioned in this section. Fill the unused
space with a chassis ground plane, and connect it to the metal card bracket and any connector shields/grounds.
4. Keep the current paths of separate board functions isolated, thereby reducing the current's travel distance. Separate
board functions are: host interface, display, digital (SRAM, EPROM, modem), and DAA. Power and ground for each of
these functions should be separate islands connected together at the power and ground source points only.
5. For serial DTE models, decouple the power cord at the power cord interface with decoupling capacitors. Methods to
decouple power lines are similar to decoupling telephone lines.
6. Connect grounds together at only one point, if possible, using a ferrite bead. Allow other points for grounds to be
connected together if necessary for EMI suppression. For ISA bus board design, include a zero ohm resistor between
digital ground and the PC mounting bracket to allow connecting digital ground to the bracket if needed.
7. Keep all ground traces as wide as possible, at least 25 mil to 50 mil.
8. Keep the traces connecting all decoupling capacitors to power and ground at their respective ICs as short and as direct
(i.e., not going through vias) as possible.
5.1.8 Crystal Circuit
1. Keep all traces and component leads connected to crystal input and output pins (i.e., XTLI and XTLO) short in order to
reduce induced noise levels and minimize any stray capacitance that could affect the crystal oscillator. Keep the XTLO
trace extremely short with no bends greater than 45 degrees and containing no vias since the XTLO pin is connected to a
fast rise time, high current driver.
2. Where a ground plane is not available, such as in a 2-layer design, tie the crystal capacitors ground paths using separate
short traces (as wide as possible) with minimum angles and vias directly to the corresponding device digital ground pin
nearest the crystal pins.
3. Connect crystal cases(s) to ground (if applicable).
4. Connect crystal capacitor ground connections directly to GND pin on the modem device. Do not use common ground
plane or ground trace to route the capacitor GND pin to the corresponding modem GND pin.
5.1.9 Standalone Modem Design with EIA/TIA-232 Interface
1. Use a metal enclosure. If a plastic enclosure is required, line the internal enclosure with metal foil or apply conductive
spray to the top and bottom covers to reduce emissions.
2. Place a common mode choke in series with each power supply line.
3. Place components close to each other and close to the EIA/TIA-232 interface cable connector.
4. Connect power and ground for all EIA/TIA-232 components to the power and ground source points via separate power
and ground traces that are not connected to the digital power and ground “except” at these source points. Power and
ground source points are the board input pins or a regulator output if used.
5. Connect the EIA/TIA-232 cable signal ground wire to digital ground.
6. Terminate the EIA/TIA-232 cable shield at the modem enclosure in one of the following manners as needed to minimize
RF emissions: leave open, connect to digital ground through a ferrite bead, or connect directly to digital ground and
provide a ferrite toroid around the EIA/TIA-232 cable close to the modem enclosure.
5.1.10 VC and VREF Circuit
1. Provide extremely short, independent paths for VC and VREF capacitor connections.
a) Route the connection from the plus terminal of the 10
µ
F VREF capacitor and one terminal of the 0.1
µ
F VREF
capacitor to the MDP VREF pin with a single trace.
Содержание RC144D
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